Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications
TL;DR: The current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories are reviewed and the challenges and opportunities are outlined.
Abstract: Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.
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TL;DR: In this article, the authors summarized some of the essential aspects of silicon-nanowire growth and of their electrical properties, including the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs-Thomson effect for the silicon wire growth velocity.
Abstract: This paper summarizes some of the essential aspects of silicon-nanowire growth and of their electrical properties. In the first part, a brief description of the different growth techniques is given, though the general focus of this work is on chemical vapor deposition of silicon nanowires. The advantages and disadvantages of the different catalyst materials for silicon-wire growth are discussed at length. Thereafter, in the second part, three thermodynamic aspects of silicon-wire growth via the vapor–liquid–solid mechanism are presented and discussed. These are the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs–Thomson effect for the silicon wire growth velocity. The third part is dedicated to the electrical properties of silicon nanowires. First, different silicon nanowire doping techniques are discussed. Attention is then focused on the diameter dependence of dopant ionization and the influence of interface trap states on the charge carrier density in silicon nanowires. It is concluded by a section on charge carrier mobility and mobility measurements.
721 citations
TL;DR: In this article, a Si nanowire based tunneling field effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure has been presented.
Abstract: This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high Ion/Ioff ratio (105), as well as low Drain-Induced Barrier Lowering of 70 mV/V.
297 citations
Cites background from "Si, SiGe Nanowire Devices by Top–Do..."
...(∼70 mV/V) is achieved as a result of excellent gate control by GAA structure [4], [11], and [12]....
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TL;DR: A bit- cost-effective technology path toward the 3D integration that requires only one critical lithography step or mask for reducing the bit-cost is demonstrated in this work.
Abstract: The three-dimensional (3D) cross-point array architecture is attractive for future ultra-high-density nonvolatile memory application. A bit-cost-effective technology path toward the 3D integration that requires only one critical lithography step or mask for reducing the bit-cost is demonstrated in this work. A double-layer HfOx-based vertical resistive switching random access memory (RRAM) is fabricated and characterized. The HfOx thin film is deposited at the sidewall of the predefined trench by atomic layer deposition, forming a vertical memory structure. Electrode/oxide interface engineering with a TiON interfacial layer results in nonlinear I–V suitable for the selectorless array. The fabricated HfOx vertical RRAM shows excellent performances such as reset current ( 108 cycles), read disturbance immunity (>109 cycles), and data retention time (>105 s @ 125 °C).
294 citations
01 Dec 2012
TL;DR: In this paper, a double-layer stacked HfOx vertical RRAM is demonstrated for 3D crosspoint architecture using a cost-effective fabrication process, and a unique write/read scheme is proposed for 3d cross-point architecture.
Abstract: Double-layer stacked HfOx vertical RRAM is demonstrated for 3D cross-point architecture using a cost-effective fabrication process. Electrode/oxide interface engineering using TiON layer results in non-linear I-V suitable for the selector-less array. The fabricated HfOx vertical RRAM shows excellent performances such as reset current ( 108 cycles), half-selected read disturbance immunity (>109 cycles), retention (>105s @125oC). Moreover, a unique write/read scheme is proposed for 3D cross-point architecture. Analysis shows that for such 3D selector-less array, a large R on (∼100kΩ) from the non-linear I-V helps reduce the sneak path current, and a low interconnect resistance using metal planes as word lines reduces the undesirable voltage drop on the interconnect. As a conservative estimate, simulation shows that Mb-scale array without cell selector is achievable.
175 citations
TL;DR: This review provides methods for the synthesis and modification of silicon nanosheets and other silicon nanomaterials with examples of their potential applications and a soft synthetic method for silicon nanOSheets with chemical surface modification in a solution process.
Abstract: Silicon nanomaterials and nanostructures exhibit different properties from those of bulk silicon materials based on quantum confinement effects. They are expected to lead to the development of new applications of silicon, in addition to wide use in semiconductor devices. Aside from industrial interest, intriguing issues of academic interest still remain with respect to the origins of their characteristic properties. Zero- and one-dimensional crystalline silicon nanomaterials have been synthesized, to date, by using many methods and there has been rapid progress in size control and modification procedures. However, there have been only a few examples of silicon nanomaterials with atomic-order thickness akin to carbon nanomaterials, such as two-dimensional silicon nanosheets. Moreover, mass production of silicon nanomaterials with relatively low cost is not easily achievable, due to the typically severe conditions required for fabrication, such as high temperature and ultralow pressure. Recently, we have developed a soft synthetic method for silicon nanosheets with chemical surface modification in a solution process. This review provides methods for the synthesis and modification of silicon nanosheets and other silicon nanomaterials with examples of their potential applications.
160 citations
References
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07 Nov 2006
657 citations
"Si, SiGe Nanowire Devices by Top–Do..." refers methods in this paper
...The bottom–up approaches involving synthesis of NWs have been extensively reviewed in the literature, for instance, by Xia et al. [11], Law et al. [19], and Lu and Lieber [ 20 ], and are not discussed in further detail in this paper....
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IBM1
TL;DR: In this paper, the authors focus on approaches to continue CMOS scaling by introducing new device structures and new materials, including high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET and strained-silicon FET.
Abstract: This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.
644 citations
"Si, SiGe Nanowire Devices by Top–Do..." refers methods in this paper
...In addition, the performance of scaled devices has been further improved by introducing stressors in the structure to improve mobility [ 2 ], [3]....
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TL;DR: It is demonstrated that the silicon nanowire devices can readily and rapidly distinguish the affinities of distinct small-molecule inhibitors and, thus, could serve as a technology platform for drug discovery.
Abstract: Development of miniaturized devices that enable rapid and direct analysis of the specific binding of small molecules to proteins could be of substantial importance to the discovery of and screening for new drug molecules. Here, we report highly sensitive and label-free direct electrical detection of small-molecule inhibitors of ATP binding to Abl by using silicon nanowire field-effect transistor devices. Abl, which is a protein tyrosine kinase whose constitutive activity is responsible for chronic myelogenous leukemia, was covalently linked to the surfaces of silicon nanowires within microfluidic channels to create active electrical devices. Concentration-dependent binding of ATP and concentration-dependent inhibition of ATP binding by the competitive small-molecule antagonist STI-571 (Gleevec) were assessed by monitoring the nanowire conductance. In addition, concentration-dependent inhibition of ATP binding was examined for four additional small molecules, including reported and previously unreported inhibitors. These studies demonstrate that the silicon nanowire devices can readily and rapidly distinguish the affinities of distinct small-molecule inhibitors and, thus, could serve as a technology platform for drug discovery.
620 citations
"Si, SiGe Nanowire Devices by Top–Do..." refers background in this paper
...Electrical sensing through change in conductance (or resistance) of Si-NW has been demonstrated successfully for metal ions [9], [10], [62], DNA [63]–[68], proteins [ 69 ]–[71], virus [72], and cells [73]....
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TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Abstract: This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.
605 citations
"Si, SiGe Nanowire Devices by Top–Do..." refers methods in this paper
...[28], [29]....
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...By utilizing such NWs as channel body, we have fabricated GAA NW-FETs [28], NW-Schottky barrier FETs [30], SONOS-type NVM cells [31], and NW logic circuits....
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TL;DR: It is demonstrated that SiNWs can be utilized to quantitate the solution-phase concentration of biomolecules at low concentrations, and the importance of surface chemistry for optimizing biomolecular sensing with silicon nanowires is demonstrated.
Abstract: The quantitative, real-time detection of single-stranded oligonucleotides with silicon nanowires (SiNWs) in physiologically relevant electrolyte solution is demonstrated. Debye screening of the hybridization event is circumvented by utilizing electrostatically adsorbed primary DNA on an amine-terminated NW surface. Two surface functionalization chemistries are compared: an amine-terminated siloxane monolayer on the native SiO2 surface of the SiNW, and an amine-terminated alkyl monolayer grown directly on a hydrogen-terminated SiNW surface. The SiNWs without the native oxide exhibit improved solution-gated field-effect transistor characteristics and a significantly enhanced sensitivity to single-stranded DNA detection, with an accompanying 2 orders of magnitude improvement in the dynamic range of sensing. A model for the detection of analyte by SiNW sensors is developed and utilized to extract DNA-binding kinetic parameters. Those values are directly compared with values obtained by the standard method of surface plasmon resonance (SPR) and demonstrated to be similar. The nanowires, however, are characterized by higher detection sensitivity. The implication is that SiNWs can be utilized to quantitate the solution-phase concentration of biomolecules at low concentrations. This work also demonstrates the importance of surface chemistry for optimizing biomolecular sensing with silicon nanowires.
508 citations