Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications
TL;DR: The current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories are reviewed and the challenges and opportunities are outlined.
Abstract: Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.
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TL;DR: In this article, the authors summarized some of the essential aspects of silicon-nanowire growth and of their electrical properties, including the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs-Thomson effect for the silicon wire growth velocity.
Abstract: This paper summarizes some of the essential aspects of silicon-nanowire growth and of their electrical properties. In the first part, a brief description of the different growth techniques is given, though the general focus of this work is on chemical vapor deposition of silicon nanowires. The advantages and disadvantages of the different catalyst materials for silicon-wire growth are discussed at length. Thereafter, in the second part, three thermodynamic aspects of silicon-wire growth via the vapor–liquid–solid mechanism are presented and discussed. These are the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs–Thomson effect for the silicon wire growth velocity. The third part is dedicated to the electrical properties of silicon nanowires. First, different silicon nanowire doping techniques are discussed. Attention is then focused on the diameter dependence of dopant ionization and the influence of interface trap states on the charge carrier density in silicon nanowires. It is concluded by a section on charge carrier mobility and mobility measurements.
721 citations
TL;DR: In this article, a Si nanowire based tunneling field effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure has been presented.
Abstract: This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high Ion/Ioff ratio (105), as well as low Drain-Induced Barrier Lowering of 70 mV/V.
297 citations
Cites background from "Si, SiGe Nanowire Devices by Top–Do..."
...(∼70 mV/V) is achieved as a result of excellent gate control by GAA structure [4], [11], and [12]....
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TL;DR: A bit- cost-effective technology path toward the 3D integration that requires only one critical lithography step or mask for reducing the bit-cost is demonstrated in this work.
Abstract: The three-dimensional (3D) cross-point array architecture is attractive for future ultra-high-density nonvolatile memory application. A bit-cost-effective technology path toward the 3D integration that requires only one critical lithography step or mask for reducing the bit-cost is demonstrated in this work. A double-layer HfOx-based vertical resistive switching random access memory (RRAM) is fabricated and characterized. The HfOx thin film is deposited at the sidewall of the predefined trench by atomic layer deposition, forming a vertical memory structure. Electrode/oxide interface engineering with a TiON interfacial layer results in nonlinear I–V suitable for the selectorless array. The fabricated HfOx vertical RRAM shows excellent performances such as reset current ( 108 cycles), read disturbance immunity (>109 cycles), and data retention time (>105 s @ 125 °C).
294 citations
01 Dec 2012
TL;DR: In this paper, a double-layer stacked HfOx vertical RRAM is demonstrated for 3D crosspoint architecture using a cost-effective fabrication process, and a unique write/read scheme is proposed for 3d cross-point architecture.
Abstract: Double-layer stacked HfOx vertical RRAM is demonstrated for 3D cross-point architecture using a cost-effective fabrication process. Electrode/oxide interface engineering using TiON layer results in non-linear I-V suitable for the selector-less array. The fabricated HfOx vertical RRAM shows excellent performances such as reset current ( 108 cycles), half-selected read disturbance immunity (>109 cycles), retention (>105s @125oC). Moreover, a unique write/read scheme is proposed for 3D cross-point architecture. Analysis shows that for such 3D selector-less array, a large R on (∼100kΩ) from the non-linear I-V helps reduce the sneak path current, and a low interconnect resistance using metal planes as word lines reduces the undesirable voltage drop on the interconnect. As a conservative estimate, simulation shows that Mb-scale array without cell selector is achievable.
175 citations
TL;DR: This review provides methods for the synthesis and modification of silicon nanosheets and other silicon nanomaterials with examples of their potential applications and a soft synthetic method for silicon nanOSheets with chemical surface modification in a solution process.
Abstract: Silicon nanomaterials and nanostructures exhibit different properties from those of bulk silicon materials based on quantum confinement effects. They are expected to lead to the development of new applications of silicon, in addition to wide use in semiconductor devices. Aside from industrial interest, intriguing issues of academic interest still remain with respect to the origins of their characteristic properties. Zero- and one-dimensional crystalline silicon nanomaterials have been synthesized, to date, by using many methods and there has been rapid progress in size control and modification procedures. However, there have been only a few examples of silicon nanomaterials with atomic-order thickness akin to carbon nanomaterials, such as two-dimensional silicon nanosheets. Moreover, mass production of silicon nanomaterials with relatively low cost is not easily achievable, due to the typically severe conditions required for fabrication, such as high temperature and ultralow pressure. Recently, we have developed a soft synthetic method for silicon nanosheets with chemical surface modification in a solution process. This review provides methods for the synthesis and modification of silicon nanosheets and other silicon nanomaterials with examples of their potential applications.
160 citations
References
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TL;DR: This work addresses one significant issue regarding surface functionalization which enables highly sensitive biomolecular sensing with SiNWs and reveals the capability of an obvious discrimination against mismatched sequences.
163 citations
TL;DR: In this article, the effects of surface roughness scattering (SRS) on the device characteristics of Si nanowire transistors (SNWTs) were theoretically investigated using a full-dimensional (3D) quantum transport simulator.
Abstract: Using a full three-dimensional (3D), quantum transport simulator, we theoretically investigate the effects of surface roughness scattering (SRS) on the device characteristics of Si nanowire transistors (SNWTs). The microscopic structure of the Si/SiO2 interface roughness is directly treated by using a 3D finite element technique. The results show that (1) SRS reduces the electron density of states in the channel, which increases the SNWT threshold voltage, and (2) the SRS in SNWTs becomes less effective when fewer propagating modes are occupied, which implies that SRS is less important in small-diameter SNWTs with few modes conducting than in planar metal-oxide-semiconductor field-effect-transistors with many transverse modes occupied.
162 citations
TL;DR: Comparison of the experimental data with simulations based on a semiclassical, ballistic transport model suggests that these sub-100 nm Ge/Si NWFETs with integrated high-kappa gate dielectric operate near the ballistic limit.
Abstract: Ge/Si core/shell nanowires (NWs) are attractive and flexible building blocks for nanoelectronics ranging from field-effect transistors (FETs) to low-temperature quantum devices. Here we report the first studies of the size-dependent performance limits of Ge/Si NWFETs in the sub-100 nm channel length regime. Metallic nanoscale electrical contacts were made and used to define sub-100 nm Ge/Si channels by controlled solid-state conversion of Ge/Si NWs to NiSixGey alloys. Electrical transport measurements and modeling studies demonstrate that the nanoscale metallic contacts overcome deleterious short-channel effects present in lithographically defined sub-100 nm channels. Data acquired on 70 and 40 nm channel length Ge/Si NWFETs with a drain−source bias of 0.5 V yield transconductance values of 78 and 91 µS, respectively, and maximum on-currents of 121 and 152 µA. The scaled transconductance and on-current values for a gate and bias voltage window of 0.5 V were 6.2 mS/µm and 2.1 mA/µm, respectively, for the 4...
161 citations
01 Dec 2006
TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
160 citations
"Si, SiGe Nanowire Devices by Top–Do..." refers background or methods in this paper
...NW FETs show excellent gate control, near-ideal subthreshold behavior, high ION/IOFF ratio, and high drive current [21], [27]–[ 29 ]....
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...The inset shows the NW channel before poly-gate deposition. Reprinted with permission from [ 29 ]....
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...(b) Drain current characteristics showing that high drive currents are possible in GAA FETs. Reprinted with permission from [ 29 ]....
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...The wires have been carefully released by etching away the grown oxide in dilute HF [28], [ 29 ]....
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...For instance, we obtained ION values of 2.4 and 1.3 mA/μm, DIBL values of 8 and 13 mV/V, and SS of 60 and 65 mV/dec for NMOS and PMOS, respectively [ 29 ]....
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TL;DR: This work describes an approach to the generation of well-defined nanowire network structures on almost any solid material, up to macroscopic sample sizes, and produces nanowires with diameter <16 nm, both singly and as networks.
Abstract: There is continued interest in finding quicker and simpler ways to fabricate nanowires, even though research groups have been investigating possibilities for the past decade. There are two reasons for this interest: first, nanowires have unusual properties—for example, they show quantum-mechanical confinement effects1, they have a very high surface-to-volume ratio, enabling them to be used as sensors2, and they have the ability to connect to individual molecules3. Second, no simple method has yet been found to fabricate nanowires over large areas in arbitrary material combinations. Here we describe an approach to the generation of well-defined nanowire network structures on almost any solid material, up to macroscopic sample sizes. We form the nanowires within cracks in a thin film. Such cracks have a number of properties that make them attractive as templates for nanowire formation: they are straight, scalable down to nanometre size, and can be aligned (by using microstructure to give crack alignment via strain). We demonstrate the production of nanowires with diameter <16 nm, both singly and as networks; we have also produced aligned patterns of nanowires, and nanowires with individual contacts.
152 citations
"Si, SiGe Nanowire Devices by Top–Do..." refers background in this paper
...NWs have also been synthesized in the “microcracks” induced in the thin films using stress for templated growth [18]....
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