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Proceedings ArticleDOI

Si1-xGex Nanowire Arrays for Thermoelectric Power Generation

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TLDR
In this article, the authors show the fabrication and thermoelectric characterisation of SiGe nanowire arrays (NWAs), which are arrays of millions of parallel upstanding upstanding nanowires attached to Si bulk, rather than single NWs as studied before.
Abstract
Thermoelectricity offers an excellent clean energy generation opportunity and has attracted renewed attention in the last few decades. The low conversion efficiency and high costs currently limit its practical application. Much effort is still needed to enhance its efficiency and reduce its cost. Nanostructures have been proven to greatly enhance the thermoelectric figure of merit (ZT) because of increased phonon scattering at the interfaces. It has been demonstrated that single Si nanowires (NWs) exhibit a 60 times higher ZT than Si bulk. Meanwhile, SiGe alloys can also reduce the thermal conductivity via alloy scattering without deteriorating the other performance parameters such as Seebeck coefficient, S and electrical conductivity, σ. SiGe NWs thus promise to offer even better thermoelectric performance than Si. In this work, we will show our recent research results on the fabrication and thermoelectric characterisation of SiGe nanowire arrays (NWAs). The NWAs are arrays of millions of parallel upstanding NWs attached to Si bulk, rather than single NWs as studied before. A Seebeck coefficient of S ≈ 1.1 mV/K is measured for the SiGe NWAs/Si bulk composite and is independent of Ge fraction, consistent with the theoretically expected value. The temperature drop across the SiGe NWA is consistently larger than across a similar Si NWA, indicating reduced thermal conductivity of the SiGe NWs.The use of SiGe improves the output power with a factor of 8 in the bulk TEG configuration. The use of SiGe NWAs in the p-leg only, increases the output power by a factor of 5 in comparison with the Si NWA TEG. These improvements are due to the reduction of the thermal conductance of the SiGe NWs and the reduction of the electrical contact resistance of the SiGe-based wires while the Seebeck coefficient remains unaffected

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Journal ArticleDOI

Thermoelectric Performance of $\hbox{Si}_{0.8} \hbox{Ge}_{0.2}$ Nanowire Arrays

TL;DR: In this paper, the output power of a thin-film thermoelectric generator consisting of a Cu-20-μm nanowire array (NWA)-Si bulk-Cu sandwich with Si or Si 0.8Ge 0.2 was measured and compared to Cu-Si bulk -Cu for small temperature differences around room temperature.
Journal ArticleDOI

n-Si–p-Si1−xGex nanowire arrays for thermoelectric power generation

TL;DR: In this article, the influence of Ge content and nanowire structures on the performance of thermoelectric devices is evaluated in measurements around room temperature, and the use of nanowires and SiGe with dimensions smaller than 30 μm is beneficial for an improvement of at least a factor of 10 in the output power.

Efficiency Improvement of Silicon Nanowire Arrays (NWAs) Thermoelectric Power Generation (TEG) by Spin On Doping (SOD)

Bin Xu, +1 more
TL;DR: In this article, a method to boost the output power of the TEG via post NWA-definition SOD is presented, which is based on a post-NWA definition of SOD.
References
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Journal ArticleDOI

Enhanced thermoelectric performance of rough silicon nanowires

TL;DR: In this article, the authors report the electrochemical synthesis of large-area, wafer-scale arrays of rough Si nanowires that are 20-300 nm in diameter.
Journal Article

Enhanced Thermoelectric Performance in Rough Silicon Nanowires

TL;DR: Electrochemical synthesis of large-area, wafer-scale arrays of rough Si nanowires that are 20–300 nm in diameter show promise as high-performance, scalable thermoelectric materials.
Journal ArticleDOI

High Power Terahertz and Millimeter-Wave Oscillator Design: A Systematic Approach

TL;DR: A systematic approach to designing high frequency and high power oscillators using activity condition is introduced, and a novel triple-push structure is introduced to realize 256 GHz and 482 GHz oscillators.
Proceedings ArticleDOI

A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna

TL;DR: A signal source operating near 410 GHz that is fabricated using low-leakage transistors in a 6 M 45 nm digital CMOS technology is reported.
Proceedings ArticleDOI

SiGe HBT technology with f T /f max of 300GHz/500GHz and 2.0 ps CML gate delay

TL;DR: In this paper, a SiGe HBT technology featuring f T /f max /BV CEO =300GHz/500GHz/1.6V and a minimum CML ring oscillator gate delay of 2.0 ps is presented.
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