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Journal ArticleDOI

SiGeO layer formation mechanism at the SiGe/oxide interfaces during Ge condensation

19 Jan 2007-Applied Physics Letters (American Institute of Physics)-Vol. 90, Iss: 3, pp 032111
TL;DR: In this paper, the fabrication process to realize high Ge content SiGe on insulator using Ge condensation technique with and without intermittent oxide etching was presented. But, the authors did not consider the problem of uncontrolled oxidation of silicon when the oxide layer is etched away.
Abstract: The letter presents the fabrication processes to realize high Ge content SiGe on insulator using Ge condensation technique with and without intermittent oxide etching. During condensation process with intermittent silicon oxide etching, the formation of an undesirable amorphous SiGeO is observed. This is due to uncontrolled oxidation of silicon when the oxide layer is etched away. In the case of Ge condensation process without oxide etching, the authors could achieve a SiGe layer with 91% Ge concentration. A crystalline SiGeO layer at the interfaces of the top silicon oxide and buried oxide with SiGe was also observed. Possible formation mechanisms of amorphous and crystalline SiGeO are presented. Ge condensation process without SiO2 etching utilizes four steps of oxidation and intermittent annealing cycles at each temperature resulted in Si0.09Ge0.91OI substrate.
Citations
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Patent
Jack T. Kavalieros1, Nancy M. Zelick1, Been-Yih Jin1, Markus Kuhn1, Stephen M. Cea1 
23 Dec 2009
TL;DR: In this paper, techniques for enabling multi-sided condensation of semiconductor fin-based transistors are described, where a fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion.
Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

129 citations

Patent
Hafez Walid M1, Chia-Hong Jan1, Curtis Tsai1, Joodong Park1, Jeng-Ya D. Yeh1 
18 Oct 2011
TL;DR: In this article, techniques for providing non-volatile antifuse memory elements and other antifusor links are disclosed, where the antifouse memory elements are configured with non-planar topology such as FinFET topology.
Abstract: Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.

46 citations

Patent
David P. Brunco1
17 Dec 2012
TL;DR: In this article, a silicon/germanium fin is formed in a layer of insulating material, wherein the fin has a first germanium concentration, recessing an upper surface of the layer of the fin so as to expose a portion of the fine-grained fin, performing an oxidation process, and removing the oxide materials from the fin that was formed during the oxidation process.
Abstract: One illustrative method disclosed herein includes forming a silicon/germanium fin in a layer of insulating material, wherein the fin has a first germanium concentration, recessing an upper surface of the layer of insulating material so as to expose a portion of the fin, performing an oxidation process so as to oxidize at least a portion of the fin and form a region in the exposed portion of the fin that has a second germanium concentration that is greater than the first germanium concentration, removing the oxide materials from the fin that was formed during the oxidation process and forming a gate structure that is positioned around at least the region having the second germanium concentration.

36 citations

Patent
23 Sep 2010
TL;DR: In this article, the authors propose a method to construct a fin from a substrate including a first material and a fin including a second material, the fin being disposed on the substrate and having a device active portion, presenting a lattice mismatch between respective crystalline structures.
Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

29 citations

Journal ArticleDOI
TL;DR: In this paper, pre-strained fin-patterned Si/SiGe multilayer structures for sub-7 nm stacked gate-all-around Si-technology transistors that have been grown onto bulk-Si, virtually relaxed SiGe, strained Silicon-On-Insulator, and compressive SiGe-on-insulator were investigated.
Abstract: Pre-strained fin-patterned Si/SiGe multilayer structures for sub-7 nm stacked gate-all-around Si-technology transistors that have been grown onto bulk-Si, virtually relaxed SiGe, strained Silicon-On-Insulator, and compressive SiGe-On-Insulator were investigated. From strain maps with a nanometer spatial resolution obtained by transmission electron microscopy, we developed 3D quantitative numerical models describing the mechanics of the structures. While elastic interactions describe every other system reported here, the patterning on the compressive SiGe-On-Insulator substrate that is fabricated by Ge-condensation results in relaxation along the semiconductor/insulator interface, revealing a latent plasticity mechanism. As a consequence, Si layers with a uniaxial stress of 1.4 GPa are obtained, bringing fresh perspectives for strain engineering in advanced devices. These findings could be extended to other semiconductor technologies.

24 citations

References
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Book
01 Jan 1986
TL;DR: Binary Alloy Phase Diagrams, Second Edition, Plus Updates, on CD-ROM offers you the same high-quality, reliable data you'll find in the 3-volume print set published by ASM in 1990.
Abstract: Gives you access to the 4,700 atomic and weight percent graphs included in the reference set Binary Alloy Phase Diagrams, Second Edition, published by ASM in 1990 - plus updates! All the data from the 3,600-page, three-volume set, abstracts of phase diagram evaluations for 3,000 binary alloy systems, special points and crystal structure tables, along with 300 recent updates from the current literature are included on one CD-ROM for ease of use and storage. Binary Alloy Phase Diagrams plus updates on CD-ROM containing all the data from Massalski's world standard, three-volume, 3,600-page Binary Alloy Phase Diagrams, Second Edition, fits in the palm of your hand! This CD includes 4,700 diagrams; abstracts of phase diagram evaluations for 3,000 binary alloy systems; special points; crystal structure tables; plus 300 recent updates from current literature. All in databases and in CD-ROM format, so it's easier to access, more flexible to use, and more efficient for you to store than ever before. Binary Alloy Phase Diagrams, Second Edition, Plus Updates, on CD-ROM, offers you the same high-quality, reliable data you'll find in the 3-volume print set published by ASM in 1990. The over 4,700 diagrams were digitized from original program graphs or redrawn from carefully selected data sources. Each diagram is in accordance to thermodynamic principles and is consistent with melting and phase-transition temperatures of the pure elements. All diagrams met strict quality standards throughout preparation. Now, the CD-ROM format puts this quality information at your fingertips. These are not scanned pages, but true, complete databases of phase diagram and crystallographic information, all in one incredibly small but powerful package, you'll wonder what you ever did without it! This new electronic format allows you to: Search for diagrams, crystal structure data, or text by keying in the alloys. Search the Master Crystal Structure Table for Intermetallic compounds with equivalent structure type, temperature, and phase width criteria. Print diagrams, text, crystal structure. Examine any new data in conjunction with the original data as presented in the print volume. Zoom in on a complicated section of the diagram for a closer look. (Vat payable on UK orders for CD products) Multi-User prices available: Contact Steve French (Customer Services Manager) Telephone: +44 (0)1462 437933; E-Mail: SFrench@ameritech.co.uk

13,433 citations

Journal ArticleDOI
TL;DR: In this paper, a strained Ge-on-insulator (GOI) structure with a 7-nm-thick Ge layer was fabricated for applications to high-speed transistors, which exhibited a single-crystal structure with the identical orientation to an original SOI substrate and a smooth Ge/SiO2 interface.
Abstract: A strained Ge-on-insulator (GOI) structure with a 7-nm-thick Ge layer was fabricated for applications to high-speed transistors. The GOI layer was formed by thermal oxidation of a strained SiGe layer grown epitaxially on a silicon-on-insulator (SOI) wafer. In transmission electron microscopy measurements, the obtained GOI layer exhibited a single-crystal structure with the identical orientation to an original SOI substrate and a smooth Ge/SiO2 interface. The rms of the surface roughness of the GOI layer was evaluated to be 0.4 nm by atomic force microscopy. The residual Si fraction in the GOI layer was estimated to be lower than the detection limit of Raman spectroscopy of 0.5% and also than the electron energy loss spectroscope measurements of 3%. It was found that the obtained GOI layer was compressively strained with a strain of 1.1%, which was estimated by the Raman spectroscopy. Judging from the observed crystal quality and the strain value, this technique is promising for fabrication of high-mobilit...

288 citations

Journal ArticleDOI
TL;DR: In this article, a novel fabrication technique for relaxed and thin SiGe layers on buried oxide (BOX) layers, i.e., SiGe on insulator (SGOI), with a high Ge fraction is proposed and demonstrated for application to strained-Si metal-oxide-semiconductor field effect transistors (MOSFETs).
Abstract: A novel fabrication technique for relaxed and thin SiGe layers on buried oxide (BOX) layers, ie, SiGe on insulator (SGOI), with a high Ge fraction is proposed and demonstrated for application to strained-Si metal-oxide-semiconductor field effect transistors (MOSFETs) This fabrication technique is based on the high-temperature oxidation of the SGOI layers with a lower Ge fraction It is found that Ge atoms are rejected from the oxide and condensed in the SGOI layers The conservation of the total amount of Ge atoms in the SGOI layer is confirmed by structural and compositional analyses of dry-oxidized SGOI layers at 1050°C of different initial thicknesses and oxidation times Using this technique, a 16-nm-thick SGOI layer with the Ge fraction as high as 057 is successfully obtained The Ge profiles across the SGOI layers are quite uniform and the layers are almost completely relaxed Significant dislocation generation in the SGOI layer is not observed after the oxidation This is a promising technique for application to sub-100 nm fully-depleted silicon-on-insulator (SOI) MOSFETs with strained-Si or SiGe channels

200 citations

Journal ArticleDOI
TL;DR: In this paper, the structural properties of Si/Ge dot multilayers are characterized in Raman spectra. And the results show that the Si-Ge and Ge-Si modes can be used as an efficient way to determine the average strain and composition in uncorrelated small-sized si/Ge dots in which the mean strain field is close to biaxial case.
Abstract: A detailed Raman characterization of the structural properties of as-grown and annealed self-assembled Si/Ge dot multilayers is reported in this paper. Several new modes in as-grown or annealed Si/Ge dots and a frequency splitting of $4.2{\mathrm{cm}}^{\ensuremath{-}1}$ between the longitudinal (LO) and transversal optical (TO) Ge-Ge modes in as-grown Si/Ge dots are observed in Raman spectra. An average Ge content of 0.8 and lateral strain of $\ensuremath{-}3.4%$ are consistently obtained from these spectral features for as-grown Si/Ge dots with a lateral size of about 20 nm and a height of about 2 nm. It suggests that a certain amount of intermixing between Si spacer layers and Si/Ge dots takes place for the Si/Ge dot multilayers. The annealing behavior of the Ge-Si mode in Si/Ge dots indicates that the observed sharp Ge-Si mode is a Ge-Si alloy mode within the core regions of Si/Ge dots, rather than a Ge-Si interface mode in the interface regions of dots. The phonon strain-shift coefficients of the Ge-Ge and Ge-Si modes are determined for the small-sized Si/Ge dots with a high Ge content under a biaxial strain condition. The results show that the LO-TO frequency splitting of the Ge-Ge mode and the frequencies of the Ge-Ge and Ge-Si modes can be used as an efficient way to determine the average strain and composition in uncorrelated small-sized Si/Ge dot multilayers in which the mean strain field is close to the biaxial case.

110 citations

Journal ArticleDOI
TL;DR: In this article, the diffusion of Ge atoms overwhelms the Ge accumulation at the top thermal oxide∕SiGe interface, resulting in a flat Ge profile in the SGOI layer.
Abstract: The movement of Ge during Ge condensation in SiGe-on-insulator (SGOI) fabrication is studied based on the competition between the diffusion of Ge atoms and accumulation of Ge atoms. The diffusion of Ge atoms overwhelms the Ge accumulation at the top thermal oxide∕SiGe interface, resulting in a flat Ge profile in the SGOI layer. However, the opposite result is found at the bottom SiGe∕buried-oxide (BOX) interface. The Ge diffusion towards the BOX is blocked because of the much smaller diffusion coefficient of Ge in the BOX than that in the SiGe layer. The Ge accumulation effects are more dominant than the diffusion of Ge, and so Ge atoms pile up near the BOX giving rise to an abrupt profile. The disappearance of the SiGe lattice structure near the SiGe∕BOX interface is also found in the sample oxidized for a longer time due to the reduction of the melting point of SiGe alloys with higher Ge fractions.

32 citations