Silicon Nanowire Field Effect Devices By Top-Down CMOS Technology

2007 IEEE Device Research Conference: Tour de Force Multigate and Nanowire Metal Oxide Semiconductor Field-Effect Transistors and Their Application.

Abstract: Scaling of the conventional planar complementary metal oxide semiconductor (CMOS) faces many challenges. Top-down fabricated gate-all-around Si nanowire FinFETs, which are compatible with the CMOS processes, offer an opportunity to circumvent these limitations to boost the device scalability and performance. Beyond applications in CMOS technology, the thus fabricated Si nanowire arrays can be explored as biosensors, providing a possible route to multiplexed label-free electronic chips for molecular diagnostics.

Strained Silicon Nanowire Transistors With Germanium Source and Drain Stressors

Abstract: We report the first demonstration of pure germanium (Ge) source/drain (S/D) stressors on the ultranarrow or ultrathin Si S/D regions of nanowire FETs with gate lengths down to 5 nm. Ge S/D compressively strains the channel to provide up to ~ 100% I Dsat enhancement. We also introduce a novel Melt-Enhanced Dopant diffusion and activation technique to form fully embedded Si0.15Ge0.85 S/D stressors in nanowire FETs, further boosting the channel strain and achieving ~ 125% I Dsat enhancement.

Vertical Nanowire Gate-All-Around p-type Tunneling Field-Effect Transistor With Si 0.8 Ge 0.2 /Si Heterojunction

Abstract: We present a CMOS compatible p-type gate-all-around (GAA) vertical silicon nanowire tunneling field effect transistor (TFET) featuring Si0.8Ge0.2 source with silicon channel. Besides heterojunction on source side, the highly abrupt doping profile at source-to-channel junction is achieved by low temperature dopant segregation. The fabricated devices display subthreshold slope (SS) as low as 30mV/dec over one decade of drain current, which remains below 60 mV/dec over 3 decades. In addition, our TFET showed reasonable Ion/Ioff ratio of (10 4 ) and low drain induced barrier lowering (DIBL) of 40 mV/V.

Drain current characteristics of silicon nanowire field effect transistor

Abstract: This paper presents the simulation study of characteristics of an 11nm Silicon Nanowire Field Effect Transistor. This architecture is applicable for ultra-scaled devices up to sub-11 nm technology nodes that employ silicon films of a few nm in thickness. The defining characteristics of ultrathin silicon devices such as Short Channel Effects and Quasi-Ballistic transport are considered in modelling the device. Device geometries play a very important role in short channel devices, and hence their impact on drain current is also analyzed by varying the silicon and oxide thickness. The proposed simulation model gives a detailed outlook on the characteristics of the nanowire device in the inversion regime.

Epitaxial core–shell and core–multishell nanowire heterostructures

Abstract: Semiconductor heterostructures with modulated composition and/or doping enable passivation of interfaces and the generation of devices with diverse functions. In this regard, the control of interfaces in nanoscale building blocks with high surface area will be increasingly important in the assembly of electronic and photonic devices. Core-shell heterostructures formed by the growth of crystalline overlayers on nanocrystals offer enhanced emission efficiency, important for various applications. Axial heterostructures have also been formed by a one-dimensional modulation of nanowire composition and doping. However, modulation of the radial composition and doping in nanowire structures has received much less attention than planar and nanocrystal systems. Here we synthesize silicon and germanium core-shell and multishell nanowire heterostructures using a chemical vapour deposition method applicable to a variety of nanoscale materials. Our investigations of the growth of boron-doped silicon shells on intrinsic silicon and silicon-silicon oxide core-shell nanowires indicate that homoepitaxy can be achieved at relatively low temperatures on clean silicon. We also demonstrate the possibility of heteroepitaxial growth of crystalline germanium-silicon and silicon-germanium core-shell structures, in which band-offsets drive hole injection into either germanium core or shell regions. Our synthesis of core-multishell structures, including a high-performance coaxially gated field-effect transistor, indicates the general potential of radial heterostructure growth for the development of nanowire-based devices.