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Proceedings ArticleDOI

Silicon Nanowire Field Effect Devices By Top-Down CMOS Technology

18 Jun 2007-pp 47-48

AbstractThere has been tremendous advancement in the development of novel nano-technologies for future CMOS nanoelectronics. The challenges and opportunities have been widely discussed with the focus on the choice of materials, processes of implementation and innovative non-classical device architectures to continuously meet the scaling requirements. Among the non-classical device architectures, Gate All Around (GAA) FET with nanowire (NW) channel body offers the ultimate electro-static control and thus has the potential to push the gate length to few nanometers. The key challenge for NWs to be widely adopted in semiconductor industry is that they have to be formed by large scale manufacturing methods. Especially, for CMOS applications, the methods should not lead to contamination issues.

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Citations
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Journal ArticleDOI
01 Aug 2007-ACS Nano
TL;DR: Top-down fabricated gate-all-around Si nanowire FinFETs, which are compatible with the CMOS processes, offer an opportunity to circumvent limitations to boost the device scalability and performance.
Abstract: Scaling of the conventional planar complementary metal oxide semiconductor (CMOS) faces many challenges. Top-down fabricated gate-all-around Si nanowire FinFETs, which are compatible with the CMOS processes, offer an opportunity to circumvent these limitations to boost the device scalability and performance. Beyond applications in CMOS technology, the thus fabricated Si nanowire arrays can be explored as biosensors, providing a possible route to multiplexed label-free electronic chips for molecular diagnostics.

13 citations


Cites background or methods from "Silicon Nanowire Field Effect Devic..."

  • ...A Novel Electrode-Induced Strain Engineering for High Performance SOI FinFET Utilizing Si (110) Channel for Both N and PMOSFETs....

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  • ...have separately demonstrated gateall-around (GAA) Si nanowire MOSFETs.(1,4,5) In these demonstrations, Si nanowires were fabricated using a top-down approach on either thin-body SOI or bulk Si substrates....

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  • ...used to strain-engineer Si FinFETs to improve carrier mobility.(1,7) The work func-...

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  • ...derivatized the surfaces of oxidized Si nanowires with probe biomolecules of peptide nucleic acid to produce highly sensitive label-free biosensor arrays.(1,11) Here, they take advantage of the large surface-to-volume ratio of the nanowires, and hence the high sensitivity of channel conductance to small changes in surface charge with biomolecule binding....

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  • ...mance results for Si nanowire MOSFETs fabricated using a top-down approach.(1) Si...

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Journal ArticleDOI
Abstract: We report the first demonstration of pure germanium (Ge) source/drain (S/D) stressors on the ultranarrow or ultrathin Si S/D regions of nanowire FETs with gate lengths down to 5 nm. Ge S/D compressively strains the channel to provide up to ~ 100% I Dsat enhancement. We also introduce a novel Melt-Enhanced Dopant diffusion and activation technique to form fully embedded Si0.15Ge0.85 S/D stressors in nanowire FETs, further boosting the channel strain and achieving ~ 125% I Dsat enhancement.

9 citations


Cites background from "Silicon Nanowire Field Effect Devic..."

  • ...to their direct compatibility with conventional CMOS process flow [1]–[5]....

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01 Jan 2012
Abstract: We present a CMOS compatible p-type gate-all-around (GAA) vertical silicon nanowire tunneling field effect transistor (TFET) featuring Si0.8Ge0.2 source with silicon channel. Besides heterojunction on source side, the highly abrupt doping profile at source-to-channel junction is achieved by low temperature dopant segregation. The fabricated devices display subthreshold slope (SS) as low as 30mV/dec over one decade of drain current, which remains below 60 mV/dec over 3 decades. In addition, our TFET showed reasonable Ion/Ioff ratio of (10 4 ) and low drain induced barrier lowering (DIBL) of 40 mV/V.

3 citations


Cites background from "Silicon Nanowire Field Effect Devic..."

  • ...Moreover, the vertical nanowire provides high density of integration which leads to more number of devices per unit area [17]....

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Journal ArticleDOI
Abstract: This paper presents the simulation study of characteristics of an 11nm Silicon Nanowire Field Effect Transistor. This architecture is applicable for ultra-scaled devices up to sub-11 nm technology nodes that employ silicon films of a few nm in thickness. The defining characteristics of ultrathin silicon devices such as Short Channel Effects and Quasi-Ballistic transport are considered in modelling the device. Device geometries play a very important role in short channel devices, and hence their impact on drain current is also analyzed by varying the silicon and oxide thickness. The proposed simulation model gives a detailed outlook on the characteristics of the nanowire device in the inversion regime.

2 citations


Cites background from "Silicon Nanowire Field Effect Devic..."

  • ...More recently, researchers have developed gate-all around (GAA) FET [5-7], where the channel body is all covered by gate and thus provide better electrostatic control of the channel....

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References
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Journal ArticleDOI
07 Nov 2002-Nature
TL;DR: The synthesis of core–multishell structures, including a high-performance coaxially gated field-effect transistor, indicates the general potential of radial heterostructure growth for the development of nanowire-based devices.
Abstract: Semiconductor heterostructures with modulated composition and/or doping enable passivation of interfaces and the generation of devices with diverse functions. In this regard, the control of interfaces in nanoscale building blocks with high surface area will be increasingly important in the assembly of electronic and photonic devices. Core-shell heterostructures formed by the growth of crystalline overlayers on nanocrystals offer enhanced emission efficiency, important for various applications. Axial heterostructures have also been formed by a one-dimensional modulation of nanowire composition and doping. However, modulation of the radial composition and doping in nanowire structures has received much less attention than planar and nanocrystal systems. Here we synthesize silicon and germanium core-shell and multishell nanowire heterostructures using a chemical vapour deposition method applicable to a variety of nanoscale materials. Our investigations of the growth of boron-doped silicon shells on intrinsic silicon and silicon-silicon oxide core-shell nanowires indicate that homoepitaxy can be achieved at relatively low temperatures on clean silicon. We also demonstrate the possibility of heteroepitaxial growth of crystalline germanium-silicon and silicon-germanium core-shell structures, in which band-offsets drive hole injection into either germanium core or shell regions. Our synthesis of core-multishell structures, including a high-performance coaxially gated field-effect transistor, indicates the general potential of radial heterostructure growth for the development of nanowire-based devices.

1,969 citations