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Proceedings ArticleDOI

Simulation and optimization of the power distribution network in VLSI circuits

05 Nov 2000-pp 481-486
TL;DR: Simulation techniques to estimate the worst-case voltage variation using an RC model for the power distribution network and frequency domain sensitivity analysis based decoupling capacitance placement for reducing the voltage variation in the power Distribution network are presented.
Abstract: In this paper, we present simulation techniques to estimate the worst-case voltage variation using an RC model for the power distribution network. Pattern independent maximum envelope currents are used as a periodic input for performing the frequency-domain steady-state simulation of the linear RC circuit to evaluate the worst-case instantaneous voltage drop for the RC power distribution networks. The proposed technique unlike existing techniques, is guaranteed to give the maximum voltage drop at nodes in the RC power distribution network. We present experimental results to compare the frequency-domain and time-domain simulation techniques for estimating the maximum instantaneous voltage drop. We also present frequency domain sensitivity analysis based decoupling capacitance placement for reducing the voltage variation in the power distribution network. Experimental results on circuits extracted from layout are presented to validate the simulation and optimization techniques.

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Citations
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Journal ArticleDOI
25 Sep 2006
TL;DR: A brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power V LSI circuits is presented.
Abstract: The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods

420 citations

Journal ArticleDOI
TL;DR: This paper presents a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid, and shows that even for a 60 million-node power grid, the approach allows for an efficient analysis, whereas previous approaches have been unable to handle power grids of such size.
Abstract: Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated on industrial designs. It is shown that even for a 60 million-node power grid, our approach allows for an efficient analysis, whereas previous approaches have been unable to handle power grids of such size.

284 citations


Cites background from "Simulation and optimization of the ..."

  • ...Manually generated “hot loops,” an extensive set of input vectors and statically generated worst-case current profiles [ 6 ], [10]‐[13] are some of the alternatives that address the worst-case coverage issue....

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Proceedings ArticleDOI
01 Jun 2000
TL;DR: A new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid, and a novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superiorSparsification for a specified error.
Abstract: Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated through the analysis of case studies of several multi-million node power grids, extracted from real microprocessor and DSP designs.

204 citations

Book
11 Mar 2009
TL;DR: EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits.
Abstract: This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book. Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes Table of Contents Chapter 1: Introduction Chapter 2: Fundamentals of CMOS Design Chapter 3: Design for Testability Chapter 4: Fundamentals of Algorithms Chapter 5: Electronic System-Level Design and High-Level Synthesis Chapter 6: Logic Synthesis in a Nutshell Chapter 7: Test Synthesis Chapter 8: Logic and Circuit Simulation Chapter 9:?Functional Verification Chapter 10: Floorplanning Chapter 11: Placement Chapter 12: Global and Detailed Routing Chapter 13: Synthesis of Clock and Power/Ground Networks Chapter 14: Fault Simulation and Test Generation.

200 citations

Journal ArticleDOI
TL;DR: Compared to postfloorplan approach, the peak power-supply noise can be reduced by as much as 40% and the decap budget can be reduction by asMuch as 21% by using noise-aware floorplanning methodology.
Abstract: We investigate the problem of decoupling capacitance (decap) allocation for power supply noise suppression at floorplan level. First, we assume that a floorplan is given and consider the decap placement as a postfloorplan step. Second, we consider the decap placement as an integral part of a floorplanning methodology (noise-aware floorplanning). In both cases, the objective is to minimize the floorplan area while suppressing the power supply noise below the specified limit. Experimental results on MCNC benchmark circuits show that, for postfloorplan decap placement, the white space allocated for decap is about 6%-9% of the chip area for the 0.25-/spl mu/m technology. The power-supply noise is kept below the specified limit. Compared to postfloorplan approach, the peak power-supply noise can be reduced by as much as 40% and the decap budget can be reduced by as much as 21% by using noise-aware floorplanning methodology. The total area is also reduced due to the reduced total decap budget gained from reduced power supply noise.

171 citations


Cites background from "Simulation and optimization of the ..."

  • ...In the past, decap optimization has been investigated at circuit level or system level [11], [12] with the assumption that there is always white (empty) space available for decap....

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References
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Book
31 Aug 1983
TL;DR: Computer methods for circuit analysis and design, Computer methods forcircumference and design , مرکز فناوری اطلاعات و £1,000,000; اوشاوρزی £1,500,000.
Abstract: Computer methods for circuit analysis and design , Computer methods for circuit analysis and design , مرکز فناوری اطلاعات و اطلاع رسانی کشاورزی

1,144 citations

Book
01 Jan 1990
TL;DR: This chapter discusses the design and implementation of the APFT Time-Point Selection Algorithm, and some of the methods used to construct the Transform Matrix, which simplifies the selection process.
Abstract: 1. Introduction.- 2. Motivation.- 3. Background.- 4. Time-Domain Methods.- 5. Harmonic Balance Theory.- 6. Implementing Harmonic Balance.- 7. Mixed Frequency-Time Method.- 8. Comparisons.- 9. Summary.- Appendix A. Nomenclature.- Appendix B. APFT Time-Point Selection.- 1. Matrix Formulation.- 1.1. Previous Work.- 1.2. Condition Number and Orthonormality.- 1.3. Condition Number and Time-Point Selection.- 1.4. Condition Number and Aliasing.- 2. Near-Orthogonal Selection Algorithm.- 2.1. Time-Point Selection.- 2.2. Constructing the Transform Matrix.- 2.3. APFT Algorithm Results.- Appendix C. Arc-Length Continuation.

512 citations

Proceedings ArticleDOI
Howard H. Chen1, David D. Ling1
13 Jun 1997
TL;DR: A new design methodology to analyzethe on-chip power supply noise for high-performance microprocessors based on an integrated package-level and chip-level power bus model, and a simulated switching circuit model for each functional block offers the most complete and accurate analysis of Vdd distribution.
Abstract: This paper describes a new design methodology to analyzethe on-chip power supply noise for high-performance microprocessors.Based on an integrated package-level andchip-level power bus model, and a simulated switching circuitmodel for each functional block, this methodology offersthe most complete and accurate analysis of Vdd distributionfor the entire chip. The analysis results not only providedesigners with the inductive ΔI noise and the resistive IRdrop data at the same time, but also allow designers to easilyidentify the hot spots on the chip and ΔV across the chip.Global and local optimization such as buffer sizing, powerbus sizing, and on-chip decoupling capacitor placement canthen be conducted to maximize the circuit performance andminimize the noise.

325 citations

Proceedings ArticleDOI
01 May 1998
TL;DR: A methodology for the design and analysis of power grids in the PowerPC™ microprocessors covering the need for power grid analysis across all stages of the design process is presented.
Abstract: We present a methodology for the design and analysis of power grids in the PowerPC/sup TM/ microprocessors. The methodology covers the need for power grid analysis across all stages of the design process. A case study showing the application of this methodology to the PowerPC/sup TM/ 750 microprocessor is presented.

190 citations


"Simulation and optimization of the ..." refers methods in this paper

  • ...Use of average currents or current values obtained by simulation [1, 2, 3, 4 , 5, 6] for a small number of input vectors is not guaranteed to give the worst-case voltage drop....

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  • ...Simulation based methods that are used to estimate the macro-block current waveforms [1, 2, 3, 4 , 5, 6] and techniques that implicitly search the exponential search space for maximum current [8, 9] can only generate a lower bound estimate of the maximum current envelope given nite computational resources....

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  • ...All existing techniques [1, 2, 3, 4 , 5, 6] and the proposed technique use the hierarchical abstraction with minor variations....

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  • ...Since we use the MCE, the IR drop solution would be an upper-bound and is an improvement over the techniques proposed in [1, 2, 3, 4 ]....

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  • ...The power-bus analysis techniques [1, 2, 3, 4 ], compute the IR drop at nodes in the power distribution network by using the macro-block currents as a DC current obtained heuristically, or a DC current obtained by logic simulations for a few vectors or a transient current waveform obtained by simulations for a few vectors....

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Journal ArticleDOI
TL;DR: A pattern-independent, linear time algorithm (iMax) that estimates at every contact point, an upper bound envelope of all possible current waveforms that result by the application of different input patterns to the circuit is proposed.
Abstract: Currents flowing in the power and ground (P&G) buses of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Excessive voltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in switching speeds. Maximum current estimates are needed at every contact point in the buses to study the severity of the voltage drop problems and to redesign the supply lines accordingly. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible input patterns, this problem has, for a long time, remained largely unsolved. In this paper, we propose a pattern-independent, linear time algorithm (iMax) that estimates at every contact point, an upper bound envelope of all possible current waveforms that result by the application of different input patterns to the circuit. The algorithm is extremely efficient and produces good results for most circuits as is demonstrated by experimental results on several benchmark circuits. The accuracy of the algorithm can be further improved by resolving the signal correlations that exist inside a circuit. We also present a novel partial input enumeration (PIE) technique to resolve signal correlations and significantly improve the upper bounds for circuits where the bounds produced by iMax are not tight. We establish with extensive experimental results that these algorithms represent a good time-accuracy trade-off and are applicable to VLSI circuits. >

156 citations