Simulation of voltage based efficient fire sensor on FPGA using SSTL IO standards
22 Apr 2014-pp 21-24
TL;DR: This work has used Verilog as HDL and Xilinx ISE 14.6 as simulator to design the voltage based efficient fire sensor and has used four different kinds of Stub Series Terminated Logic (SSTL)IO standards.
Abstract: In this paper an approach is made to design the voltage based efficient fire sensor and for that reason we have used four different kinds of Stub Series Terminated Logic (SSTL)IO standards. Airflow and heat sink are main parameters while analyzing the thermal dissipation in the circuit. In this work we have taken two values for LFM i.e. 250, 500 and three profiles for heat sink are taken, these are low profile, medium profile and high profile. When the voltage sensor is operating at 1THz and LFM is 250 with low profile heat sink, junction temperature of SSTL135_DCI is reduced up to 5.12% 6.03% and 20.77% as compared to SSTL12, SSTL12_DCI and SSTL135_R respectively. Under same operating frequency and heat sink profile with LFM as 500, we are achieving 3.69%, 5.22% and 17.99% less junction power reduction in SSTL135_DCI with respect to SSTL12, SSTL12_DCI and S S TL135_Rrespectively. This design is implemented on Kintex-7 FPGA, XC7K70T device and −3 speed grades. In this work we have used Verilog as HDL and Xilinx ISE 14.6 as simulator.
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31 Aug 2015
TL;DR: Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper and can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius.
Abstract: In this paper we have designed an energy efficient multiplier using Nikhilam Navatashcaramam Dashatah Vedic technique. Vedic mathematics consists of 16 sutras and these sutras were used by our ancient scholars for doing there calculation faster, when there were no computers and calculators. Nikhilam Navatasaman is a Sanskrit word which menas “all from 9 and the last from 10”. In today’s work the demand is high speed, efficiency and should take lesser time. Appling these Vedic techniques reduces the system complexity, execution time, area, power and is stable and hence is efficient method. In this paper we have designed an energy efficient multiplier that consists of three inputs and one output. The temperature has been kept constant that is 25 degree Celsius. Airflow has been kept 250 LFM and medium Heat sink. IO Standards has been varied in order to achieve an energy efficient device. In this paper we have taken HSTL (High Speed Transceiver Logic) IOSTANDARD. In order to achieve speed and high performance in addition to energy efficiency, HSTL IO standard is used. HSTL family consists of HSTL _I, HSTL_II, HSTL_I_18 and HSTL_II_18, HSTL_I_12 and the analysis has been done on these IO standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA.
20 citations
Cites background from "Simulation of voltage based efficie..."
...Airflow and heat sink are main parameters while analyzing the thermal dissipation in the circuit [5]....
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04 Apr 2015
TL;DR: Voltage scaling is used to make the counter design as an energy efficient design and it has been observed that when different powers have been measured at different frequencies and different voltages in case of counter the significant power dissipation is in case clocks and IOs.
Abstract: In this work, we are using voltage scaling to make the counter design as an energy efficient design. The 74163 counter is a 4-bit fully synchronous counter that is available in both TTL and CMOS logic families. In addition to performing the counting function, it can be cleared or loaded in parallel. It has been observed that when different powers have been measured at different frequencies and different voltages in case of counter the significant power dissipation is in case clocks and IOs. Out of which in case of clock the maximum power dissipation is in range of 12.126W to 35.056W at which is in case of 1THz when measured at different voltage levels where as in case of IOs the maximum power dissipation is in range of 20.636W to 25.031W. Which is again in case of 1THz when measured at different voltage levels. There is not much significant change in case of signal and leakage power at different voltage levels. The maximum total power dissipation is in range of 33.887W to 67.986W at frequency of 1THz when operated at different voltages. Also there can be 94.45% to 99.61% reduction in total power dissipation if we operate on frequency of 1MHz instead of frequency of 1THz at different Voltage levels.
17 citations
Cites methods from "Simulation of voltage based efficie..."
...Voltage scaling is used in mobile battery charge controller sensor [3], voltage sensor for fire detection [5], J.K. Flip Flops[7], energy efficient FIR Filter design [7], voltage based fire sensor [8], reliable ALU design [9] and Green GCD Generator [10]....
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01 Nov 2014
TL;DR: This work is operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use, using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator.
Abstract: Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the impedance of line, port and device of our design under consideration. Therefore, selection of energy efficient SSTL I/O standard among available different class of SSTL logic family in FPGA, plays a vital role to achieve energy efficiency in design under test (DUT). Here, DUT is ROM. ROM is an integral part of processor. Therefore, energy efficient design of RAM is a building block of energy efficient processor. We are using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator. We are operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use. When there is no demand of peak performance, then we can save 74.5% clock power, 75% signal power, and 30.83% I/O power by operating our device with 1GHz frequency in place of 4GHz. There is no change in clock power and signal power but SSTL2_H_DCI having 80.24% 83.38% 62.92% and 76.52% and 83.03% more I/O power consumption with respect to SSTL2_I, SST18_I, SSTL2_I_DCI, SSTL2_II, and SSTL15 respectively at 3.3GHz.
14 citations
Cites background from "Simulation of voltage based efficie..."
...1818978-9-3805-4416-8/15/$31.00 c©2015 IEEE The primary purpose of using HSTL I/O standard is to avoid transmission line reflection by matching the impedance of transmission line, device, input port and output port....
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01 Dec 2014
TL;DR: In this article, the authors used voltage scaling and frequency scaling to reduce power dissipation on Virtex-6 FPGA on 10MHz device operating frequency and showed that the reduction in dissipation can be achieved by scaling the voltage from 3V to 1V, where intermediate values are 25V, 2V, 18V and 15V.
Abstract: In this work, we are using voltage scaling and frequency scaling In voltage scaling, voltage is scaled from 3V to 1V, where intermediate values are 25V, 2V, 18V and 15V In frequency scaling, frequency is scaled from 1 MHz to 1 THz, where intermediate values are 10 MHz, 100 MHz, 1 GHz, 10 GHz and 100 GHz When we scale down device operating frequencies from 1THz to 1GHz, there is 729% reduction in power dissipation on Virtex-6 FPGA When we scale down device operating frequencies from 1THz to 1GHz, there is 9875% reduction in power dissipation on Virtex-4 FPGA When we scale down device supply voltage from 3V to 25V, 2V, 18V and 1V, there is 8223%, 9683%, 9845% and 99% reduction in power dissipation respectively on Virtex-6 FPGA on 10MHz device operating frequency When we scale down device supply voltage from 3V to 25V, 2V, 18V and 1V, there is 7442%, 9267%, 9471% and 9766% reduction in power dissipation respectively on Virtex-6 FPGA on 1THz device operating frequency
7 citations
31 Aug 2015
TL;DR: Frequency is varied to obtain power consumption of Wrist Watch, capacitance scaling is used and there is no change in clock power, logic power and signal power, and to design an energy efficient device.
Abstract: In this paper, we have designed an energy efficient wrist watch on 28nm FPGA. The code has been implemented in Xilinx ISE Design Suite 14.2. The device used is XC7K160T, package used is FBG676 and it is working on -3 speed grade. The wrist band will take the blood pressure as input and will tell about the state of the person wearing it. The design supports Internet of things service that’s why IP addresses are involved. This wrist band design is very helpful in biomedical areas. Research is in progress in this field. In this paper frequency is varied to obtain power consumption of Wrist Watch. Airflow has been kept 250 LFM and medium Heat sink. IO Standards has been varied in order to achieve an energy efficient device. Main emphasis has been done on MOBILE_DDR, LVTTL, HSUL_12, HSTL_I, LVCMOS33 and SSTL15 IO Standards. To design an energy efficient device we are using capacitance scaling and the capacitance is scaled down from 100pF to 20pF. During capacitance scaling, we observe that there is no change in clock power, logic power and signal power. Thermal Aware design is current research area. Analysis has been at two temperatures that is at 25 degree Celsius and at 50 degree Celsius. At the end we can conclude that the maximum power is consumed at 2.2GHz and minimum power is consumed at 1.2GHz. In respect of capacitance maximum power is consumed at 100pF and minimum power is consumed at 20pF at both temperatures at 25 degree Celsius and 50 degree Celsius.
6 citations
References
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01 Dec 2013
TL;DR: In this article, a green image ALU is designed in Xilinx ISE 14.6 using different IO standard of SSTL in 40nm Virtex-6 and Spartan-6 FPGA.
Abstract: In this paper, green Image ALU is designed in Xilinx ISE 14.6 using different IO standard of SSTL in 40nm Virtex-6 and Spartan-6 FPGA. We are comparing different SSTL IO standard to get reduction in IO power. We accomplish energy efficiency with respect to low voltage impedance, by using SSTL technology. In this entire work, we are using different classes of SSTL and observe that when image ALU operates at 1THz device operating frequency with SSTL18_I_DCI I/O Standard using virtex-6 FPGA, there is 45.55% decrease in IO power and 20.50% in Clock power as compared to SSTL18_II IO Standard. Similarly when we operate Image ALU at 1THz using Spartan-6, there is 33.31% reduction in IO power of SSTL18_I with respect to SSTL18_II Standard. There are 16 different arithmetic and logic operations in Image ALU. The Clock power, Logic power and Signal power of Image ALU remains same using Spartan-6 I/O Standard.
22 citations
"Simulation of voltage based efficie..." refers methods in this paper
...In [5], with the help of different types of SSTL IO standards, it is analyzed that on operating image ALU with 1THz frequency on virtex-6 FPGA clock power and IO power of SSTL18_I_DCI is reduced up to 45....
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TL;DR: In this article, the authors used Voltage Scaling as energy efficient technique to make energy efficient MBCCS, where they scale down supply voltage from 1V to 0.1V, where 0.9V, 0.8V, 1V, 2V, 3V, 4V, 5V, 6V, 7V, 8V, 9V, 10V, 11V, 12V, 14V, 15V, 16V, 17V, 18V, 19V, 20V, 21V, 22V, 23V, 24
Abstract: In this work, we are using Voltage Scaling as energy efficient technique to make energy efficient MBCCS. In MBCCS, whenever voltage or current of battery will under the threshold level the battery will continuing the charge if more than voltage or current threshold then battery will invoke Ring Overcharge Alarm. In Voltage Scaling, we scale down supply voltage from 1V to 0.1V, where 0.9V, 0.8V, 0.7V, 0.6V, 0.5V, 0.4V, 0.3V and 0.2V are intermediate supply voltage value. There is 92.72%, 87.50%, 98.77% and 68.24% reduction in Clock Power, Logic Power, Signal Power and IO Power on 1 THz device operating frequency when voltage is scale down from 1V to 0.1V with step size of 0.1V.
18 citations
19 May 2013
TL;DR: This paper describes a reference-free voltage sensor implemented using a speed independent (SI) SRAM cell and an inverter chain that provides accurate measurements of Vdd over this operating range with a precision range from 50mV to 10mV.
Abstract: In future systems with relatively unreliable and unpredictable energy sources such as harvesters, the system Vdd may become non-deterministic. Reliable and accurate on-chip voltage sensors are therefore indispensible for the power and computation management of such systems. Stable and known references are also difficult to obtain in this environment. This paper describes a reference-free voltage sensor implemented using a speed independent (SI) SRAM cell and an inverter chain. It can work under a wide range of Vdd, and provides accurate measurements of Vdd over this operating range with a precision range from 50mV to 10mV. Unlike existing methods, the voltage information is directly generated as a digital code without any analog circuits. This is realized by exploiting the inherently different latency behaviors of different types of circuits under different Vdd.
17 citations
"Simulation of voltage based efficie..." refers background in this paper
...The work in [7] tells about referencefree voltage sensor and that operate in huge range of supply voltage and it can operate in range of 50mV to 10mV....
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20 Mar 2001
TL;DR: In this paper, the authors determine the optimization point for several different fan-heat sink combinations and find a theoretical methodology that will simulate the natural phenomena, thus obtaining the ability to optimize the system without experimentation.
Abstract: In portable electronics, the thermal management system must be optimized to attain the highest performance in the given space and under the given constraints The greater the number of fins, the higher the surface area will be, thus aiding forced convection However, by increasing the number of fins within the same available space, the performance of the fans or blowers will be degraded The primary goal of the paper is to determine the optimization point for several different fan-heat sink combinations The secondary goal is to find a theoretical methodology that will simulate the natural phenomena, thus obtaining the ability to optimize the system without experimentation
14 citations
"Simulation of voltage based efficie..." refers background in this paper
...Reference [9], evaluates the improvements with various fan heat sink combinations and design a theoretical procedure....
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02 Oct 1988
TL;DR: In this article, an integrated SAW (surface acoustic wave) voltage sensor is presented, based on the SAW oscillator system, with features such as high sensitivity, broad measuring range, high input impedance, and direct voltage-to-frequency conversion.
Abstract: An integrated SAW (surface acoustic wave) voltage sensor is presented, based on the SAW oscillator system, with features such as high sensitivity, broad measuring range, high input impedance, and direct voltage-to-frequency conversion. The dual oscillator system possesses the additional advantage of temperature compensation. The piezoelectric zinc oxide layer is not only used for the excitation and detection of surface acoustic waves, but also as a very thin dielectric (approximately 18 mu m). As a result, the generation of high electric fields by low voltages enables the design of high-sensitivity sensors. The sensor shows a short-term stability of 2 Hz at an operating frequency of 72 MHz and a drift of about 100 Hz/hr. The sensitivity for DC signals is 60 Hz/V. Frequency modulation of the output signal in response of an AC input has been detected for frequencies up to 50 Hz. An important technological step is the application of a passivation layer on top of the zinc oxide layer. Two passivating materials and processes have been examined. >
10 citations