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Proceedings ArticleDOI

Sine and cosine generator using CORDIC algorithm implemented in ASIC

01 Oct 2015-pp 1-3
TL;DR: To generate sine and cosine function using CORDIC algorithm, this algorithm uses simple addition, subtraction and shift operation in place of multiplication, it is a hardware efficient algorithm.
Abstract: Objective of this paper is to generate sine and cosine function using CORDIC algorithm. CORDIC comes fast when to evaluate DSP algorithms uses basic function such as addition, multiplication, trigonometric functions etc. This algorithm uses simple addition, subtraction and shift operation in place of multiplication, it is a hardware efficient algorithm. Here the inputs are vector coordinate and desired angle of rotation. The results show that sine and cosine values of the outputs. The flow of this paper starts with RTL simulation using IES, synthesis using RTL Compiler and finally physical design using SoC Encounter.
Citations
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Proceedings ArticleDOI
01 Aug 2017
TL;DR: The objective of this paper is to propose a method for QPSK modulation which further reduces power consumption, reduces memory requirement and improves the speed of operation by increasing the maximum operating frequency.
Abstract: Quadrature Phase Shift Keying (QPSK) modulation is a popular digital modulation technique. Though it consumes less power and is quite compact as compared to other digital modulation technique, the objective of this paper is to propose a method for QPSK modulation which further reduces power consumption, reduces memory requirement and improves the speed of operation by increasing the maximum operating frequency. The proposed modulation method brings changes in Direct Digital Frequency Synthesizer (DDFS) block in the conventional QPSK modulation technique, which results in the improvement of various performance parameters. Here, the input is the bit sequence generated by a pseudorandom number (PN) generator and the output is the QPSK modulated signal.

6 citations


Cites background or methods from "Sine and cosine generator using COR..."

  • ...The algorithm is derived from general rotation theorem [2],[3]:...

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  • ...Optimized QPSK Modulator-II To further optimize the QPSK modulator, CORDIC algorithm was used to generate sine and cosine values for the angles given by phase accumulator [3]....

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  • ...This algorithm uses iterative method for performing vector rotation by performing shifts and adds [2],[3]....

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  • ...The iterative rotation can be explained as [2],[3]:...

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  • ...CORDIC algorithm works on the principle of vector rotation [3]....

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Proceedings ArticleDOI
01 Dec 2017
TL;DR: The main idea of this new CORDIC algorithm is to use an area efficient carry select adder (CSLA), instead of using a normal adder, which can achieve fast arithmetic operation in various data processing techniques.
Abstract: In this paper, we have designed an efficient CORDIC algorithm, which is used to minimize the CORDIC rotation angle with the help of several rotations. The main idea of this new CORDIC algorithm is to use an area efficient carry select adder (CSLA), instead of using a normal adder. This adder can achieve fast arithmetic operation in various data processing techniques. Finally, the comparison of various parameters like area, power and delay are calculated and they are reduced in the proposed method when compared to the existing method.

2 citations

Journal Article
TL;DR: The objective of the thesis is to address the problem of clock skew between two different modules in modern day microprocessors or any high speed digital design, which is caused by different clock tree insertion delays and due to process, voltage and temperature (PVT) variations.
Abstract: In system-on-chip (SoC) design, a buffered clock distribution network is typically used to drive the large clock load. Chip design involves a clock alignment step, which equalizes the delay from the clock source to each and every clock target (flip flops, latches, or other memory elements). Accurate clock alignment is important, because unwanted differences or uncertainties in clock network delays may degrade performance or cause functional errors. Clock distribution and alignment has become an increasingly challenging problem in very large scale integration (VLSI) design, consuming an increasing portion of resources such as wiring area, power, and design time. The clock skew problem is more prominent in the case of an SoC (System-on-Chip) device where many blocks need to communicate each other and have different internal clock tree delays depending on their clock tree depth. The objective of the thesis is to address the problem of clock skew between two different modules in modern day microprocessors or any high speed digital design, which is caused by different clock tree insertion delays and due to process, voltage and temperature (PVT) variations. This paper presents an automatic clock skew control scheme in order to mitigate the misalignment of the clocks in the different regions of SoC. The stated approach requires Delay Lock Loop (DLL) to add or subtract the delay to keep the clocks continuously aligned to a common reference clock delay. For Simulation results of the design Cadence compilercverilog and simvision have been used.
Proceedings ArticleDOI
27 May 2022
TL;DR: A sinusoidal waveform generator is implemented using an efficient 16-stage pipelined CORDIC architecture with a very small look-up table (LUT) to improve the output frequency and the accuracy.
Abstract: Frequency synthesizer has been used in numerous communication applications. This is acknowledged as the heart of the electronics systems. Numerically controlled oscillator (NCO) is the primary part of this frequency synthesizer, which helps in generating high precision & high frequency signal. One of the best suited methods to empower the NCO is CORDIC algorithm. CORDIC (Coordinate Rotation Digital Computer) algorithm is one of the well-known methods used for the trigonometric & arithmetic calculation and applications of digital signal processing. This algorithm can work with higher efficiency for the signal generation & hardware utilization. CORDIC architecture is used in the NCO, which is the central part of DDFS (Direct Digital Frequency Synthesis) to produce analog signal. Here in this paper, a sinusoidal waveform generator is implemented using an efficient 16-stage pipelined CORDIC architecture with a very small look-up table (LUT). The architecture is designed, and its RTL simulation is carried out using Xilinx Vivado. The purpose of the work is to improve the output frequency and the accuracy. The architecture had been implemented on a Xilinx Spatran-6 (XC6SLX9) FPGA & the final results showed that the proposed pipelined architecture is capable of generating a maximum output frequency of 157.684 MHz with less than 1% (approximately 0.34%) of error.
References
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Journal ArticleDOI
TL;DR: A new scheme, the modified vector rotational CORDIC (MVR-CORDIC) algorithm, to improve the speed performance of CORDic algorithm and provide a systematic design flow as well as the optimization procedure in the application of MVR- cORDIC algorithm.
Abstract: The CORDIC algorithm is a well-known iterative method for the computation of vector rotation. However, the major disadvantage is its relatively slow computational speed. For applications that require forward rotation (or vector rotation) only, we propose a new scheme, the modified vector rotational CORDIC (MVR-CORDIC) algorithm, to improve the speed performance of CORDIC algorithm. The basic idea of the proposed scheme is to reduce the iteration number directly while maintaining the SQNR performance. This can be achieved by modifying the basic microrotation procedure of CORDIC algorithm. Meanwhile, three searching algorithms are suggested to find the corresponding directional and rotational sequences so as to obtain the best SQNR performance. Three SQNR performance refinement schemes are also suggested in this paper. Namely, the selective prerotation scheme, selective scaling scheme, and iteration-tradeoff scheme. They can reduce and balance the quantization errors encountered in both microrotation and scaling phases so as to further improve the overall SQNR performance. Then, by combining these three refinement schemes, we provide a systematic design flow as well as the optimization procedure in the application of MVR-CORDIC algorithm. Finally, we present two VLSI architectures for the MVR-CORDIC algorithm. It shows that by using the proposed MVR-CORDIC algorithm, we can save 50% execution time in the iterative CORDIC structure, or 50% hardware complexity in the parallel CORDIC structure compared with the conventional CORDIC scheme.

89 citations


"Sine and cosine generator using COR..." refers methods in this paper

  • ...CORDIC ALGORITHM A detailed survey of various CORDIC algorithm implementations is available in [1-8]....

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Journal ArticleDOI
TL;DR: This paper proposes a new vector rotational scheme called mixed-scaling-rotation coordinate rotational digital computer (MSR-CORDIC) algorithm, which can eliminate the overhead of the scaling operations that are inevitable in existing CORDIC algorithms; hence, it can significantly reduce the total iteration number so as to improve the speed performance.
Abstract: The coordinate rotational digital computer (CORDIC) algorithm is a well-known iterative arithmetic for performing vector rotations in many digital signal processing (DSP) applications. However, the large number of iteration is a major disadvantage of this algorithm for its speed performance. Many researchers have proposed schemes to reduce the number of iterations. Nevertheless, in performing the existing CORDIC algorithms, the norm of the vector is usually enlarged so that extra scaling operations are required to deliver the normalized output. In this paper, we merge the two operation phases (microrotations and scaling phases) and propose a new vector rotational scheme called mixed-scaling-rotation coordinate rotational digital computer (MSR-CORDIC) algorithm. It can eliminate the overhead of the scaling operations that are inevitable in existing CORDIC algorithms; hence, it can significantly reduce the total iteration number so as to improve the speed performance. The proposed MSR-CORDIC can be applied to DSP applications, in which the rotational angles are known in advance [e.g., twiddle factor in fast Fourier transform (FFT) processor designs]. Moreover, most CORDIC algorithms generally suffer from the roundoff noise in the fixed-wordlength implementations. We also propose two schemes to control and reduce the impairment. Our simulation results show that the MSR-CORDIC algorithm can enhance the signal-to-quantization-noise ratio (SQNR) performance by controlling the internal dynamic range. We also investigate the first- and second-order statistical properties, including the mean and variance of the SQNR. Simulation results show that the MSR-CORDIC can enhance SQNR performance of both first- and second-order statistical properties. At the VLSI architecture level, we proposed a generalized MSR-CORDIC engine for the tradeoff between hardware complexity and quantization error performance. It can further reduce the hardware complexity when compared with the newly proposed extend elementary angle set CORDIC algorithm . The MSR-CORDIC scheme has been applied to a variable-length FFT processor design , and results in significant hardware reduction in implementing the twiddle factor operations.

81 citations


"Sine and cosine generator using COR..." refers methods in this paper

  • ...CORDIC ALGORITHM A detailed survey of various CORDIC algorithm implementations is available in [1-8]....

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Journal ArticleDOI
TL;DR: The authors have proposed a new hybrid CORDIC algorithm which reduces the iteration to (3\mbin/8) + 1 for \mbin bit precision including the scale factor calculation and compensation.
Abstract: CORDIC (COordinate Rotational DIgital Computer) has gained momentum for decades because of its less hardware complexity in real time applications such as communication systems, signal and image processing. The main drawbacks of CORDIC algorithm are increased number of iterations, scale factor calculation and compensation. Researchers have worked to reduce the latency in terms of number of iterations and minimize the critical path with redundant arithmetic and fast adders. Some researchers have proposed algorithms to reduce the number of iterations to ${\mbi{n}}/{\bf 2}$ plus additional iterations including rotation and scale factor calculation and compensation for ${\mbi{n}}$ bit precision. However, to the knowledge of the authors, no further reduction of number of iterations has been addressed. In this context, the authors have proposed a new hybrid CORDIC algorithm which reduces the iteration to $({\bf 3}{\mbi{n}}/{\bf 8}) + {\bf 1}$ for ${\mbi{n}}$ bit precision including the scale factor calculation and compensation. The proposed algorithm and its first order architecture have been compared with the existing low latency CORDIC algorithms in terms of iterations, hardware complexity and critical delay. The scope of this work is to present a novel hybrid CORDIC algorithm along with first order hardware architecture.

41 citations


"Sine and cosine generator using COR..." refers methods in this paper

  • ...CORDIC ALGORITHM A detailed survey of various CORDIC algorithm implementations is available in [1-8]....

    [...]

Journal ArticleDOI
TL;DR: The novel annihilation-reordering look-ahead technique is proposed as an attractive technique for pipelining of Givens rotation (or CORDIC)-based adaptive filters and is employed to develop fine-grain pipelined QR decomposition-based RLS adaptive filters.
Abstract: The novel annihilation-reordering look-ahead technique is proposed as an attractive technique for pipelining of Givens rotation (or CORDIC)-based adaptive filters. Unlike the existing relaxed look-ahead, the annihilation-reordering look-ahead does not depend on the statistical properties of the input samples. It is an exact look-ahead based on CORDIC arithmetic, which is known to be numerically stable. The conventional look-ahead is based on multiply-add arithmetic. The annihilation-reordering look-ahead technique transforms an orthogonal sequential adaptive filtering algorithm into an equivalent orthogonal concurrent one by creating additional concurrency in the algorithm. Parallelism in the transformed algorithm is explored and different implementation styles including pipelining, block processing, and incremental block processing are presented. Their complexities are also studied and compared. The annihilation-reordering look-ahead is employed to develop fine-grain pipelined QR decomposition-based RLS adaptive filters. Both QRD-RLS and inverse QRD-RLS algorithms are considered. The proposed pipelined architectures can be operated at arbitrarily high sample rate without degrading the filter convergence behavior. Stability under finite-precision arithmetic are studied and proved for the proposed architectures. The pipelined CORDIC-based RLS adaptive filters are then employed to develop high-speed linear constraint minimum variance (LCMV) adaptive beamforming algorithms. Both QR decomposition-based minimum variance distortionless response (MVDR) realization and generalized sidelobe canceller (GSC) realization are presented. The complexity of the pipelined architectures are analyzed and compared. The proposed architectures can be operated at arbitrarily high sample rate and consist of only Givens rotations, which can be scheduled onto CORDIC arithmetic-based processors.

40 citations


Additional excerpts

  • ...It uses fixed shift register at every stage of pipelined [9-10]....

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Journal ArticleDOI
TL;DR: This paper introduces a new design concept called Angle Quantization (AQ), which can be used as a design index for vector rotational operation, where the rotational angle is known in advance, and establishes a unified design framework for cost-effective low-latency rotational algorithms and architectures.
Abstract: Vector rotation is the key operation employed extensively in many digital signal processing applications. In this paper, we introduce a new design concept called Angle Quantization (AQ). It can be used as a design index for vector rotational operation, where the rotational angle is known in advance. Based on the AQ process, we establish a unified design framework for cost-effective low-latency rotational algorithms and architectures. Several existing works, such as conventional COordinate Rotational Digital Computer (CORDIC), AR-CORDIC, MVR-CORDIC, and EEAS-based CORDIC, can be fitted into the design framework, forming a Vector Rotational CORDIC Family. Moreover, we address four searching algorithms to solve the optimization problem encountered in the proposed vector rotational CORDIC family. The corresponding scaling operations of the CORDIC family are also discussed. Based on the new design framework, we can realize high-speed/low-complexity rotational VLSI circuits, whereas without degrading the precision performance in fixed-point implementations.

28 citations


Additional excerpts

  • ...It uses fixed shift register at every stage of pipelined [9-10]....

    [...]