Single-phase seven-level stack multicell converter using level shifting SPWM technique
07 Jun 2016-pp 1-5
TL;DR: In this article, a single-phase seven-level stack multicell converter (SMC) is presented, which provides a viable solution for multilevel converter, where only two DC sources are needed for any number of levels.
Abstract: This paper presents a single-phase seven-level stack multicell converter (SMC) which provides a viable solution for multilevel converter. Conventional cascaded multilevel inverter (MLI) removes the drawbacks of clamping diodes and clamping capacitors topologies. However, in a cascaded MLI number of voltage source and power switches increases as the number of level increases. The main advantage of single-phase SMC converter is only two DC sources are needed for any number of levels. Level shifting SPWM technique has been incorporated to achieve gate pulses, in which carrier wave of 20kHz is compared with 50Hz sinusoidal reference wave at a modulation index of 1 and 0.9. Total harmonic distortion (THD) for SMC converter is achieved at 1.55% and 5.26% with and without filter respectively. The seven-level SMC topology is simulated in MATLAB/SIMULINK and simulation results are provided to verify the performance.
Citations
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TL;DR: Analytical and simulation results prove the robustness and correctness of the technique proposed in this paper, and only exact solutions to the low-order harmonics elimination for Cascaded H-bridge inverter are reported for all modulation indices.
Abstract: Considering the aim of having low switching losses, especially in medium-voltage and high-power converters, the pre-programmed pulse width modulation technique is very useful because the generated harmonic content can be known in advance and optimized. Among the different low switching frequency techniques, the Selective Harmonics Elimination (SHE) modulation method is most suitable because of its direct control over the harmonic spectrum. This paper proposes a method for obtaining multiple solutions for selectively eliminating specific harmonics in a wide range of modulation indices by using modified Newton–Raphson (NR) and pattern generation techniques. The different pattern generation and synthesis approach provide more degrees of freedom and a way to operate the converter in a wide range of modulation. The modified Newton–Raphson technique is not complex and ensures fast convergence on a solution. Moreover, multiple solutions are obtained by keeping a very small increase in the modulation index. In the previous methods, solutions were not obtainable at all modulation indices. In this paper, only exact solutions to the low-order harmonics elimination for Cascaded H-bridge inverter are reported for all modulation indices. Analytical and simulation results prove the robustness and correctness of the technique proposed in this paper.
35 citations
01 May 2017
TL;DR: In this paper, a Transistor Clamped Five Level Inverter using Non-Inverting Double Reference Single Carrier PWM (NIDRSC PWM) Technique is presented.
Abstract: This treatise deals with Transistor Clamped Five Level Inverter using Non-Inverting Double Reference Single Carrier PWM (NIDRSC PWM) Technique. Conventional or two level inverter have drawbacks like: i) Requirement of fast switching devices, ii) Very high dv/dt, iii) High Electromagnetic Interferences (EMI), iv) Bulky filters, v) Faster heating of switches, and vi) Not suitable for high voltage applications. Multilevel Inverters (MLIs) are engaged to conquer the drawbacks of conventional two levels inverter. MLIs generate an AC voltage using small voltage steps obtained with the help of DC supplies or capacitor banks. To design the proposed five level inverter five numbers of power control switches and eight diodes are required. The proposed inverter circuitry is investigated by using Non-Inverting Double Reference Single Carrier PWM (NIDRSC PWM) Technique in terms of harmonics content in output waveform. Under-modulation (modulation Index = 0.85), unity (modulation Index =1) and over-modulation (modulation Index = 1.25) PWM signal is obtained to drive control switches. Simulation results will confirm the functionality, design and operation of the proposed MLI and NIDRSC PWM Technique.
12 citations
01 Aug 2018
TL;DR: A 7-level inverter with reduced number of switches for photovoltaic applications with reduction in the number of power semiconductor switches in proposed multilevel inverter overall switching power losses, circuit complexity, gate driver requirements and cost of the system can be reduced.
Abstract: In the present scenario of increasing power demand and depletion of fossil fuel results in the research advancements in the field of renewable energy sources. Among various types of renewable energy sources, photovoltaic related applications are gaining importance. DC-AC converters play a very prominent role in photovoltaic system in efficient power delivering for various applications. This paper proposed a 7-level inverter with reduced number of switches for photovoltaic applications. Unipolar Single Reference Multicarrier Sinusoidal Pulse Width Modulation (U-SR-MC-SPWM) technique is used for the purpose of gate pulse generation for the proposed multilevel inverter. A comparative study of seven-level cascaded multilevel inverter and a proposed multilevel inverter is carried out. Simulation and power quality analyses of both multilevel inverters are performed in MATLAB/Simulink platform version 2016(a). It is noticed that the total harmonic distortion is slightly more of the proposed multilevel inverter when compared with cascaded h-bridge inverter. But, with the reduction in the number of power semiconductor switches in proposed multilevel inverter overall switching power losses, circuit complexity, gate driver requirements and cost of the system can be reduced. The simulation results always show a good agreement with the proposed approach.
6 citations
Cites background from "Single-phase seven-level stack mult..."
...In the scenario, multilevel inverters [12]-[13] can be used which will be able to generate output with reduced harmonic content which can be easily filtered out....
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...SEVEN-LEVEL PROPOSED MULTILEVEL INVERTER WITH REDUCED NUMBER OF SWITCHES Other than the basic multilevel inverter topologies like diode-clamped multilevel inverter, flying-capacitor multilevel inverter [6] and cascaded H-bridge inverter, there are others topologies are also being developed and used in many highpower applications [12]-[16]....
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01 Jun 2017
TL;DR: In this paper, a hexagonal space vector hysteresis current control (SVHCC) for Z-source neutral-point clamped multilevel inverters (Z-NP-MLI) with DC-link capacitors balancing is presented.
Abstract: Z-source neutral-point clamped multilevel inverter (Z-NP-MLI) used in solar grid connected applications due to their better performance related to conventional inverters. Normally, current controller based Pulse Width Modulation (PWM) approach is expected for any grid connected system. The space vector pulse width modulation (SVPWM) strategy is a prominent modulation technique for Z-source multilevel inverters (MLIs) due to their appropriate voltage vector selection opportunity. Previous publications have shown the control of a ZNPMLI inverter using the SVPWM with and without modification of shoot through switching. However, the current controller based SVPWM is not attempted. This paper presents hexagonal space vector hysteresis current control (SVHCC) for ZNPMLI with DC-link capacitors balancing. This proposed SVHCC scheme uses reduced shoot through switching and finding the current reference based on the error. With respect to the error vector position, the choice of the adjacent vector is acted to minimize the error vector. In addition to the error vector selection, the capacitor voltage is also equilibrated by controlling the degree of freedom existing in selecting the switching vectors. The proposed scheme is asserted through MATLAB/Simulink and validated. The results are confirming the advantages of the proposed current control method and the line voltage and output current THD profile is lesser than conventional methods.
5 citations
Cites methods from "Single-phase seven-level stack mult..."
...Here, totally 24 ST (12 TST and 12 BST) are used in SV switching state [20-25]....
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01 Jan 2018
TL;DR: In this article, the authors proposed PS, POD, PD carrier shifting PWM algorithms for DC-MLI to tumbling the induced circulating current (CC) in inverter-fed electrical drives.
Abstract: Reduction in circulating current is one of the major considerations in inverter-fed electrical drives. Diode-clamped MLI (DC-MLI) enables higher output current per phase, thereby rating of the drive gets increased effectiveness. Various methods of triggering in the inverter legs create a better voltage profile and lead to the enabling of circulating current in the drive system. The induced circulating current (CC) flows through the apparatus neutral (N), and supply ground (G) is caused by the existence of parasitic capacitance. This circulating current may cause potential danger, especially when parasitic capacitance poses large. In the past, different modulation techniques and conversion topologies have been introduced to minimize the flow of circulating current. However, these techniques lead to complexity, high cost, low voltage profile, and efficiency due to lower modulation parameters. This paper proposes PS, POD, PD carrier shifting PWM algorithms for DC-MLI to tumbling the CC. The performances of the proposed algorithm, in terms of CC, THD, losses, and efficiencies are analyzed theoretically and are validated via simulation and experimental results.
5 citations
References
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TL;DR: The most important topologies like diode-clamped inverter (neutral-point clamped), capacitor-Clamped (flying capacitor), and cascaded multicell with separate DC sources are presented and the circuit topology options are presented.
Abstract: Multilevel inverter technology has emerged recently as a very important alternative in the area of high-power medium-voltage energy control. This paper presents the most important topologies like diode-clamped inverter (neutral-point clamped), capacitor-clamped (flying capacitor), and cascaded multicell with separate DC sources. Emerging topologies like asymmetric hybrid cells and soft-switched multilevel inverters are also discussed. This paper also presents the most relevant control and modulation methods developed for this family of converters: multilevel sinusoidal pulsewidth modulation, multilevel selective harmonic elimination, and space-vector modulation. Special attention is dedicated to the latest and more relevant applications of these converters such as laminators, conveyor belts, and unified power-flow controllers. The need of an active front end at the input side for those inverters supplying regenerative loads is also discussed, and the circuit topology options are also presented. Finally, the peripherally developing areas such as high-voltage high-power devices and optical sensors and other opportunities for future development are addressed.
6,472 citations
08 Oct 1995
TL;DR: This paper presents three multilevel voltage source converters: (1) diode-clamp, (2) flying-capacitors, and (3) cascaded-inverters with separate DC sources.
Abstract: Multilevel voltage source converters are emerging as a new breed of power converter options for high-power applications. The multilevel voltage source converters typically synthesize the staircase voltage wave from several levels of DC capacitor voltages. One of the major limitations of the multilevel converters is the voltage unbalance between different levels. The techniques to balance the voltage between different levels normally involve voltage clamping or capacitor charge control. There are several ways of implementing voltage balance in multilevel converters. Without considering the traditional magnetic coupled converters, this paper presents three recently developed multilevel voltage source converters: (1) diode-clamp, (2) flying-capacitors, and (3) cascaded-inverters with separate DC sources. The operating principle, features, constraints, and potential applications of these converters are discussed.
3,232 citations
TL;DR: A new multilevel converter topology that has many steps with fewer power electronic switches results in reduction of the number of switches, losses, installation area, and converter cost.
Abstract: This paper introduces a new multilevel converter topology that has many steps with fewer power electronic switches. The proposed circuit consists of series-connected submultilevel converters blocks. The optimal structures of this topology are investigated for various objectives, such as minimum number of switches and capacitors, and minimum standing voltage on switches for producing maximum output voltage steps. A new algorithm for determination of dc voltage sourcespsila magnitudes has also been presented. The proposed topology results in reduction of the number of switches, losses, installation area, and converter cost. The operation and performance of the proposed multilevel converter has been verified by the simulation and experimental results of a single-phase 53-level multilevel converter.
645 citations
"Single-phase seven-level stack mult..." refers background in this paper
...Further, the drawback of the large number of switches is overcome by modifying cascaded MLI discussed in [8-11]....
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TL;DR: In this article, a new topology of cascaded multilevel inverter using a reduced number of switches, insulated gate driver circuits and voltage standing on switches is proposed, which results in reduction of installation area and cost and has simplicity of control system.
475 citations
TL;DR: In this article, a novel topology for asymmetrical cascade multilevel converter is presented, which consists of series connected sub-multilevel converters blocks and it can generate more dc voltage levels than other topologies.
362 citations