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Patent

Smart card including a JTAG test controller and related methods

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TLDR
In this paper, an integrated circuit for a smart card may include a transceiver for communicating with a host device and a Joint Test Action Group (JTAG) test controller for performing at least one test operation.
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Patent

Apparatus and method for testing and debugging an integrated circuit

TL;DR: In this paper, a system including a frame capture module, a serializer, and a deserializer is described, where the serializer is configured serialize the first data frames to form serial messages that include serialized data.
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Hardware enablement using an interface

TL;DR: A hardware enablement apparatus includes a processor, and a communications interface configured for writing license data to one or more data registers and using the license data for selectively enabling, under control of the processor, hardware features associated with the data registers, at least one of which being implemented in non-volatile memory as mentioned in this paper.
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Method and apparatus for controlling enablement of JTAG interface

TL;DR: In this article, an access token server generates the access token in response to an end user providing appropriate device-specific information, such as expiration information that causes an enabled JTAG interface to revert back to its disabled status upon expiration of access token.
Patent

Apparatus and method for embedded boundary scan testing

TL;DR: In this paper, a boundary scan controller is embedded in a circuit board along with a JTAG chain having JTAG devices connected with an electrical circuit of the board, which runs boundary scan testing while holding the processor system in the reset state.
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Programmable logic device with differential communications support

TL;DR: In this article, a programmable logic device integrated circuit with differential communications circuitry is provided in which the differential communication circuitry is used to support programming, testing, and user mode operations.
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Patent

Modified computer motherboard security and identification system

TL;DR: In this article, a modified BIOS (Basic Input Output System) replaces the standard BIOS of a motherboard and allows a security engine microprocessor to take over preboot control of the computer from the motherboard CPU (Central Processing Unit), configures and operates the encryption-based security system, and enables or disables selected data storage devices and other user selectable peripherals upon start up and shut down.
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Priority encoding and decoding for memory architecture

TL;DR: In this paper, a shared resource access priority encoding/decoding and arbitration scheme takes into account varying device requirements, including latency, bandwidth and throughput, stored and dynamically updated based on changing access demand conditions.
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Dual mode smart card and associated methods

TL;DR: In this paper, a dual-mode IC is provided for operating in first mode such as an ISO mode in accordance with International Standards Organization 7816 (ISO 7816) protocol, and a second, non-ISO mode, such as a USB mode in according with Universal Serial Bus (USB) protocol.
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Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (dfd) techniques

TL;DR: In this article, a method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores, is presented.
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Smart card application development system and method

TL;DR: In this paper, an application development system for smart cards includes a computer system having a client development interface (CDI), a smart card having a SCDI and application program interface (API) functionality within the smart card operating system.