SoC: a real platform for IP reuse, IP infringement, and IP protection
TL;DR: The IP-based SoC design flow is discussed to highlight the exact locations and the nature of infringements in the flow, identifies the adversaries, categorizes these infringements, and applies strategic analysis on the effectiveness of the existing IPP techniques for these categories of infringement.
Abstract: Increased design complexity, shrinking design cycle, and low cost--this three-dimensional demandmandates advent of system-onchip (SoC) methodology in semiconductor industry. The key concept of SoC is reuse of the intellectual property (IP) cores. Reuse of IPs on SoC increases the risk of misappropriation of IPs due to introduction of several new attacks and involvement of various parties as adversaries. Existing literature has huge number of proposals for IP protection (IPP) techniques to be incorporated in the IP design flow as well as in the SoC design methodology. However, these are quite scattered, limited in possibilities in multithreat environment, and sometimes mutually conflicting. Existing works need critical survey, proper categorization, and summarization to focus on the inherent tradeoff, existing security holes, and new research directions. This paper discusses the IP-based SoC design flow to highlight the exact locations and the nature of infringements in the flow, identifies the adversaries, categorizes these infringements, and applies strategic analysis on the effectiveness of the existing IPP techniques for these categories of infringements. It also clearly highlights recent challenges and new opportunities in this emerging field of research.
Citations
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TL;DR: In the proposed technique, transformable interconnects enable an IC chip to maintain functioning in normal use and to transform its physical structure into another pattern when exposed to invasive attacks.
Abstract: Protection of intellectual property (IP) is increasingly critical for IP vendors in the semiconductor industry. However, advanced reverse engineering techniques can physically disassemble the chip and derive the IPs at a much lower cost than the value of IP design that chips carry. This invasive hardware attack—obtaining information from IC chips—always violates the IP rights of vendors. The intent of this article is to present a chip-level reverse engineering resilient design technique. In the proposed technique, transformable interconnects enable an IC chip to maintain functioning in normal use and to transform its physical structure into another pattern when exposed to invasive attacks. The newly created pattern will significantly increase the difficulty of reverse engineering. Furthermore, to improve the effectiveness of the proposed technique, a systematic design method is developed targeting integrated circuits with multiple design constraints. Simulations have been conducted to demonstrate the capability of the proposed technique, which generates extremely large complexity for reverse engineering with manageable overhead.
14 citations
Cites background from "SoC: a real platform for IP reuse, ..."
...Revealing the design details and physical implementations not only creates opportunities for illegal reproduction but also makes it easier for IP infringement, tampering, malicious alteration, and counterfeiting [1, 11, 28, 34]....
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TL;DR: This paper proposes the first known approach to protect the authorship and the usage legitimacy of NoCs using specially designed routing, square spiral routing, which exploits routing redundancy inherent in the mesh NoCs and transports packets along the paths, which have very low probability to be taken under commonly used routing algorithms.
Abstract: Intellectual property (IP) core reuse is essential for the design process of system-on-chip (SoC). Network-on-chip (NoC) has been used as an independent IP core during SoC design. However, the NoC has not been protected via IP protection and paid attention on its innovations. This paper proposes the first known approach to protect the authorship and the usage legitimacy of NoCs using specially designed routing, square spiral routing. The special routing algorithm exploits routing redundancy inherent in the mesh NoCs and transports packets along the paths, which have very low probability to be taken under commonly used routing algorithms. These unique and diverse paths are exploited in this paper to embed information of the author and identify the legal buyer of NoCs, showing high robustness and credibility. The hardware implementation of an IP-protected mesh NoC shows that the area overhead is small, which is $\sim 0.74$ %, and the power overhead is $\sim 0.52$ %, while the functionality and performance of the network is not affected. In this paper, the approach is presented for the mesh NoC, but the idea is equally applicable to other NoC topologies where the unique and diverse paths also inherently exist.
9 citations
Cites background or methods from "SoC: a real platform for IP reuse, ..."
...and become one of the major concern in the industry [1]....
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...Reuse of already designed, optimized, and verified intellectual property (IP) cores has become the pervasive practice in SoC design industry, to meet the requirements of short design time and low design cost [1]....
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...For a comprehensive review and classification of classical hardware watermarking, we refer the interested readers to [1] and [4]....
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TL;DR: A novel methodology to secure hardware accelerators against ownership threats/IP piracy using biometric fingerprinting, followed by embedding fingerprint’s digital template into the design in the form of secret biometric constraints; thereby generating a secured hardware accelerator design.
Abstract: This article presents a novel methodology to secure hardware accelerators (such as digital signal processing (DSP) and multimedia intellectual property (IP) cores) against ownership threats/IP piracy using biometric fingerprinting. In this approach, an IP vendor’s biometric fingerprint is first converted into a corresponding digital template, followed by embedding fingerprint’s digital template into the design in the form of secret biometric constraints; thereby generating a secured hardware accelerator design. The results report the following qualitative and quantitative analysis of the proposed biometric fingerprint approach: 1) impact of 11 different fingerprints on probability of coincidence (Pc) metric. As evident, the proposed approach achieves a very low Pc value in the range of 2.22E−3 to 4.35E−6. Further, the biometric fingerprint achieves total constraints size between minimum 350 bits to maximum 895 bits; 2) impact of six different resource constraints on the design cost overhead of JPEG compression hardware postembedding biometric fingerprint. As evident, for all the resource constraints implemented, the design cost overhead is 0%; and 3) comparative analysis of proposed biometric fingerprint with recent work, for five different signature strength values, in terms of Pc. As evident, the proposed approach achieves minimum 3.9E+2 times and maximum 6.9E+4 times lower Pc, when compared to recent work.
9 citations
Cites background from "SoC: a real platform for IP reuse, ..."
...encoding rules) contributing to the security of the signature are known to an attacker, it becomes ineffective, as it can easily be replicated by an attacker [24]–[26]....
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...vulnerable as it can be compromised by an attacker [24]–[26]....
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Posted Content•
TL;DR: UNTANGLE as mentioned in this paper proposes a link prediction-based attack that successfully breaks InterLock in an oracle-less setting without having access to an activated IC (oracle), since InterLock hides selected timing paths in key-controlled routing blocks.
Abstract: Logic locking aims to prevent intellectual property (IP) piracy and unauthorized overproduction of integrated circuits (ICs). However, initial logic locking techniques were vulnerable to the Boolean satisfiability (SAT)-based attacks. In response, researchers proposed various SAT-resistant locking techniques such as point function-based locking and symmetric interconnection (SAT-hard) obfuscation. We focus on the latter since point function-based locking suffers from various structural vulnerabilities. The SAT-hard logic locking technique, InterLock [1], achieves a unified logic and routing obfuscation that thwarts state-of-the-art attacks on logic locking. In this work, we propose a novel link prediction-based attack, UNTANGLE, that successfully breaks InterLock in an oracle-less setting without having access to an activated IC (oracle). Since InterLock hides selected timing paths in key-controlled routing blocks, UNTANGLE reveals the gates and interconnections hidden in the routing blocks upon formulating this task as a link prediction problem. The intuition behind our approach is that ICs contain a large amount of repetition and reuse cores. Hence, UNTANGLE can infer the hidden timing paths by learning the composition of gates in the observed locked netlist or a circuit library leveraging graph neural networks. We show that circuits withstanding SAT-based and other attacks can be unlocked in seconds with 100% precision using UNTANGLE in an oracle-less setting. UNTANGLE is a generic attack platform (which we also open source [2]) that applies to multiplexer (MUX)-based obfuscation, as demonstrated through our experiments on ISCAS-85 and ITC-99 benchmarks locked using InterLock and random MUX-based locking.
9 citations
TL;DR: A Radio Frequency Identification (RFID) based protection scheme for Intellectual Property Protection (IPP) of Static Random Access Memory (SRAM) FPGA IP cores that overcome the limitations of existing IPP techniques is proposed.
Abstract: Field-programmable gate-array (FPGA) based hardware IP cores have emerged as an integral part of modern SOC designs. IP trading plays central role in Electronic Design Automation (EDA) industry. While the potential of IP infringement is growing fast, the global awareness of IP protection remains low. In this work, we propose a Radio Frequency Identification (RFID) based protection scheme for Intellectual Property Protection (IPP) of Static Random Access Memory (SRAM) FPGA IP cores that overcome the limitations of existing IPP techniques. Here, three types of reconfigurable RFID tags is realised in order to support the incorporation of the proposed RFID based security scheme in all the reconfigurable FPGA devices of Xilinx family. Also a special tag bypass feature is employed to increase the suitability of proposed scheme as an IPP technique for reconfigurable IP cores. The proposed scheme supports safe exchange of reconfigurable FPGA IP cores between IP providers and system developers. The results derived from the testing of hardware prototype used for the evaluation of the proposed scheme are quite encouraging and shows that the proposed security feature can be incorporated into the reconfigurable IP cores of any functionality without significant performance degradation of the reconfigurable IP cores.
5 citations
References
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03 Jan 2010
TL;DR: A novel scheme to watermark the recent reconfigurable scan architectures, operating in both scan tree and single scan mode, is proposed and Experimental results on design overhead and robustness for ISCAS’89 benchmarks are encouraging.
Abstract: IP values contributed by the distinct design tools in specific design phases, are recognized by observing the signature of the owner of each tool as functional or scan mode output of the fabricated chip, for certain input vector secret to the owner. An existing approach inserts watermark through reordering of single scan chain, and solely identifies the owner of the logic design tool. Here we propose a novel scheme to watermark the recent reconfigurable scan architectures, operating in both scan tree and single scan mode. The signature of the owner of physical design tool along with that of logic design tool can separately be embedded while designing the scan tree and also verified from the packaged chip without conflict using two distinct modes. A bi-objective minimization of overhead in routing and power is supported through our scheme. Experimental results on design overhead and robustness for ISCAS’89 benchmarks are encouraging.
16 citations
"SoC: a real platform for IP reuse, ..." refers methods in this paper
...…Y Dyka and Langendoerfer 2005 [20] Y Suzuki et al. 2004 [21] Y Deng et al. 2009 [23] Y Y Castillo et al. 2007 [24] Y Abdel-Hamid et al. 2005 [25] Y Saha and Sur-Kolay 2010 [26] Y Majzoobi and Koushanfar 2009 [27] Y Agrawal et al. 2007 [28] Y Y Cui et al. 2008 [29] Y Lach et al. 2001 [30] Y Y Gu…...
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...(iii) Dynamic watermarking has been applied to reconfigurable scan architecture during physical synthesis so that desired watermark can be verified as scan outputs [26]....
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01 Jan 2001
TL;DR: A VHDL reuse component model for mixed abstraction level simulation and behavioral synthesis and a method for interface customization of soft IP cores R. Siegmund, D. Muller are presented.
Abstract: List of figures. List of tables. 1. Virtual components - from research to business J. Haase. 2. Evaluation of technology and the medea design automation roadmap J. Borel, et al. 3. Productivity in VC reuse: linking SOC platforms to abstract systems design methodology G. Martin. 4. Software IP in embedded systems C. Boke, et al. 5. ARDID: a tool and a model for the quality analysis of VHDL based designs Y. Torroja, et al. 6. A VHDL analysis environment for design reuse C. Costi, D.M. Miller. 7. Lambda-block analysis of VHDL for design reuse W. Fornaciari, et al. 8. IP retrieval by solving constraint satisfaction problems M. Koegst, et al. 9. Cryptographic reuse library A. Schubert, et al. 10.A VHDL reuse component model for mixed abstraction level simulation and behavioral synthesis C. Hansen, et al. 11. Virtual component interfaces M.M. Kamal Hashmi. 12. A method for interface customization of soft IP cores R. Siegmund, D. Muller. 13. Modeling assistant - a flexible VCM generator in VHDL A. Puika. 14. Reusing IPS to implement a SPARC(R) SOC S. Olcoz, et al. 15. Hardwwwired: using the web as repository of VHDL components A. Sarmento, et al. References. Index. Glossary.
15 citations
26 Jul 2009
TL;DR: A novel approach is proposed that converts this problem to a less challenging design quality measuring problem and shows that information can be embedded into the original graph without significant impact to the solution quality.
Abstract: For a computing system to be trusted, it is equally important to verify that the system performs no more and no less functionalities than desired. Traditional testing and verification methods are developed to validate whether the system meets all the requirements. They cannot detect the existence or show the non-existence of the unknown undesired functionalities. In this paper, we propose a novel approach that converts this problem to a less challenging design quality measuring problem. Our approach is based on information hiding and constraint manipulation of the original system design specification. We lay out the basic requirements for our approach and demonstrate it through the popular graph coloring problem. Results show that information can be embedded into the original graph without significant impact to the solution quality. However, when the same information is added to the graph modified based on our approach, there will be noticeable drop in the solution quality.
14 citations
"SoC: a real platform for IP reuse, ..." refers background in this paper
...…Y Saha and Sur-Kolay 2010 [26] Y Majzoobi and Koushanfar 2009 [27] Y Agrawal et al. 2007 [28] Y Y Cui et al. 2008 [29] Y Lach et al. 2001 [30] Y Y Gu et al. 2009 [31] Y Li and Lach 2008 [32] Y Y Potkonjak et al. 2009 [33] Y Wei et al. 2010 [34] Y Dutt and Li 2009 [35] Y Y Potkonjak 2010 [36]…...
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...Information hiding strategy to design trusted system [31] is capable of detecting possible existence of trojan horse in design IP....
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05 Mar 2007
TL;DR: A scheme SECURE_IP, which relies on the application of cryptographic principles and the watermarking techniques to provide both direct and indirect IP protection in VLSI physical design, makes unauthorized disclosure of a valuable design infeasible during its transmission, and can easily detect any alteration of the design file during transmission.
Abstract: The emerging trend of design reuse in VLSI circuits poses the threat of theft and misappropriation of intellectual property (IP) of the design. Protection of design IP is a matter of prime concern today. We propose a scheme SECURE_IP, which tackles the problem from an entirely new viewpoint. It relies on the application of cryptographic principles and the watermarking techniques to provide both direct and indirect IP protection in VLSI physical design. It makes unauthorized disclosure of a valuable design infeasible during its transmission, and can easily detect any alteration of the design file during transmission. The proposed scheme ensures authentication of the original designer as well as non-repudiation between the designer (seller) and the buyer. Illegal reselling can be efficiently detected by the proposed scheme. The algorithm SECURE_IP is tested on random and MCNC benchmark instances, and the experimental results are quite encouraging
9 citations
"SoC: a real platform for IP reuse, ..." refers background in this paper
...Illegal copies of an IP are generated due to intentional reselling of a firm/hard IP or fabrication of additional ICs in foundry [7, 8]....
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TL;DR: A new efficient watermarking system for IPP on post-layout design stage that uniquely identifies the circuit origin, yet is difficult to be detected or fabricated without the tool.
Abstract: IP (Intellectual Property) reuse plays an important role in modern IC design so that IP Protection (IPP) technique is get concerned. In this paper, we introduce a new efficient watermarking system for IPP on post-layout design stage. The signature (which indicates the designer) is encrypted with a secret key by DES (Data Encryption Standard) to produce a bit string, which is then embedded into the layout design as constraints by using a specific incremental router. Once the design is watermarked successfully, the signature can be extracted accurately by the system. The system also has a strong resistance to the attack on watermarking due to the DES functionality. This watermarking technique uniquely identifies the circuit origin, yet is difficult to be detected or fabricated without our tool. We evaluated the watermarking system on IBM-PLACE 2.0 benchmark suites. The results show the system robustness and strength: the system success probability achieves 100% in suitable time with no extra area and wire length cost on design performances.
7 citations
"SoC: a real platform for IP reuse, ..." refers methods in this paper
...Signature embedded by applying constraints in place/ route phase of physical design [8] or through incremental router [37] cannot be verified from an IC fabricated from that marked design....
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