Software implementation and performance analysis of the LTE physical layer blocks on a next generation baseband processor platform
02 May 2008-pp 1-1
TL;DR: An overview of the radio interface physical layer requirements of the current LTE standards on a second generation flexible baseband processor and the specific architectural features of the SB3500 and the compiler optimizations to yield a real time software implementation of LTE are presented.
Abstract: Summary form only given. The Third Generation Partnership Project (3GPP) has been defining the Long Term Evolution (LTE) for 3G radio access. LTE has several areas of focus. These areas include enhancement of the Universal Terrestrial Radio Access (UTRA), as well as optimization of the network architecture with HSDPA (downlink) and HSUPA (uplink). LTE project aims to ensure the continued competitiveness of the 3GPP technologies for the future LTE focuses on download rates of 100 Mbit/s, upload rates of 50 Mbit/s per 20 MHz of bandwidth, increased spectrum efficiency and sub-5ms latency for small IP packets. This paper provides an overview of the radio interface physical layer requirements. The paper then presents the implementation of the current LTE standards on a second generation flexible baseband processor. The implementation will be be limited to the receiver chain blocks and will be entirely in ANSI C, written for a fixed point digital signal processors. The underlying assumption of this implementation is to avoid any hardware accelerators that would make the hardware platform for the baseband processing standard specific. The SB3500 is the second generation of SandBlaster-based low power, high performance system on a chip (SoC) products developed to serve the software defined radio (SDR) modem applications space. It is a multi-core device, containing 3 dasiaSBXpsila DSP cores. The software implementation of LTE physical layer includes implantation of OFDM and receiver chain processing in ANSI C. The projected processing requirements of an LTE UE on the SB3500 are presented with the expected number of cores needed for the data rates analyzed. The down-sampling filter used for the initial synchronization and for the fine synchronization, FFT block, Channel estimation for each reference symbol, MIMO detector and the CRC block are included in this analysis. The specific architectural features of the SB3500 and the compiler optimizations to yield a real time software implementation of LTE are also presented.
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20 Apr 2009
TL;DR: High-end mobile phones support multiple radio standards and a rich suite of applications, which involves advanced radio, audio, video, and graphics processing, which inevitably leads to heterogeneous multi-core architectures with aggressive power management.
Abstract: High-end mobile phones support multiple radio standards and a rich suite of applications, which involves advanced radio, audio, video, and graphics processing. The overall digital workload amounts to nearly 100GOPS, from 4b integer to 24b floating-point operations. With a power budget of only 1W this inevitably leads to heterogeneous multi-core architectures with aggressive power management. We review the state-of-the-art as well as trends.
195 citations
TL;DR: Novel software architecture and load balancing for the LTE protocol stack that allows concurrent execution on a multi-core processor and thus allows for exploiting all the advantages like higher performance through parallelism at low power consumption is described.
Abstract: Coming wireless communication standards like Long Term Evolution (LTE) promise to bring a drastic increase in data rate for the end user. To facilitate this evolution, sophisticated technology for the mobile equipment is required. Most research focuses on the signal processing in the physical layer whereas the computational capabilities for protocol processing are neglected. This paper describes novel software architecture and load balancing for the LTE protocol stack that allows concurrent execution on a multi-core processor and thus allows for exploiting all the advantages like higher performance through parallelism at low power consumption. The layered protocol is developed using Specification and Description Language (SDL). In addition, the LTE protocol stack is parallelized and executed on a multi-core processor, by employing the SDL processes concurrency. Moreover, the LTE system is scheduled on multi-core by customizing the SDL scheduler to implement a data pipeline scheduler. Furthermore, a new load balancer scheme is proposed by moving the load balancer to the modem subsystem’s layer and using the SDL process migration concept. The performance of the LTE protocol implementation using the new scheme beats the classic thread migration scheme by more than 50% on single as well as multi-core platforms. The data throughput using the new scheme increases on two, three, or four cores, compared to single core, by about 195%, 290%, and 360%, respectively, and thus shows an excellent scalability for up to three cores and still giving reasonably good results for four cores. A Parallel Software Architecture for the LTE Protocol on a Multi-Core Mobile Modem
8 citations
TL;DR: The concept of cross layer design is adopted to refine the existing handover procedure specified in 802.16e MAC layer and F-HMIPv6 and shows that the proposed scheme is superior to the other scheme proposed by IETF.
Abstract: IEEE802.16e is the major global cellular wireless standard that enables low-cost mobile Internet application. However, existing handover process system still has latency affects time-sensitive applications. In this paper, the handover procedures of 802.16e and Fast Handover for Hierarchical MIPv6 (F-HMIPv6) are reconstructed to achieve a better transmission performance. The concept of cross layer design is adopted to refine the existing handover procedure specified in 802.16e MAC layer and F-HMIPv6. More specifically, layer2 and layer3 signaling messages for handover are analyzed and combined/interleaved to optimize the handover performance. Extensive simulations show that the proposed scheme in this paper is superior to the other scheme proposed by IETF.
3 citations
Additional excerpts
...Copyright © 2009 SciRes CN Keywords: handover, cross layer, 802.16e, F-HMIPv6...
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References
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Book•
31 Dec 1999
TL;DR: In this paper, the authors present a comprehensive introduction to OFDM for wireless broadband multimedia communications and provide design guidelines to maximize the benefits of this important new technology, including modulation and coding, synchronization, and channel estimation.
Abstract: From the Book:
The manifestations of the mode of goodness can be experienced when all the gates of the body are illuminated by knowledge
The Bhagavad Gita (14.11)
During the joint supervision of a Master's thesis "The Peak-to-Average Power Ratio of OFDM," of Arnout de Wild from Delft University of Technology, The Netherlands, we realized that there was a shortage of technical information on orthogonal frequency division multiplexing (OFDM) in a single reference. Therefore, we decided to write a comprehensive introduction to OFDM. This is the first book to give a broad treatment to OFDM for mobile multimedia communications. Until now, no such book was available in the market. We have attempted to fill this gap in the literature.
Currently, OFDM is of great interest by the researchers in the Universities and research laboratories all over the world. OFDM has already been accepted for the new wireless local area network standards from IEEE 802.11, High Performance Local Area Network type 2 (HIPERLAN/2) and Mobile Multimedia Access Communication (MMAC) Systems. Also, it is expected to be used for the wireless broadband multimedia communications.
OFDM for Wireless Multimedia Communications is the first book to take a comprehensive look at OFDM, providing the design guidelines one needs to maximize benefits from this important new technology. The book gives engineers a solid base for assessing the performance of wireless OFDM systems. It describes the new OFDM-based wireless LAN standards; examines the basics of direct-sequence and frequency-hopping CDMA, helpful in understanding combinations of OFDM and CDMA. It also looks at applications of OFDM, includingdigital audio and video broadcasting, and wireless ATM. Loaded with essential figures and equations, it is a must-have for practicing communications engineers, researchers, academics, and students of communications technology.
Chapter 1 presents a general introduction to wireless broadband multimedia communication systems (WBMCS), multipath propagation, and the history of OFDM. A part of this chapter is based on the contributions of Luis Correia from the Technical University of Lisbon, Portugal, Anand Raghawa Prasad from Lucent Technologies, and Hiroshi Harada from the Communications Research Laboratory, Ministry of Posts and Telecommunications, Yokosuka, Japan.
Chapters 2 to 5 deal with the basic knowledge of OFDM including modulation and coding, synchronization, and channel estimation, that every post-graduate student as well as practicing engineers must learn. Chapter 2 contains contributions of Rob Kopmeiners from Lucent Technologies on the FFT design.
Chapter 6 describes the peak-to-average power problem, as well as several solutions to it. It is partly based on the contribution of Arnout de Wild.
Basic principles of CDMA are discussed in Chapter 7 to understand multi carrier CDMA and frequency-hopping OFDMA, which are described in Chapters 8 and 9. Chapter 8 is based on the research contributions from Shinsuke Hara from the University of Osaka, Japan, a postdoctoral student at Delft University of Technology during 1995-96, Chapter 9 is based on a UMTS proposal, with main contributions of Ralf Bohnke from Sony, Germany, David Bhatoolaul and Magnus Sandell from Lucent Technologies, Matthias Wahlquist from Telia Research, Sweden, and Jan-Jaap van de Beek from Lulea University, Sweden.
Chapter 10 was written from the viewpoint of top technocrats from industries, government departments, and policy-making bodies. It describes several applications of OFDM, with the main focus on wireless ATM in the Magic WAND project, and the new wireless LAN standards for the 5 GHz band from IEEE 802.11, HIPERLAN/2 and MMAC. It is partly based on contributions from Geert Awater from Lucent Technologies, and Masahiro Morikura and Hitoshi Takanashi from NTT in Japan and California, respectively.
We have tried our best to make each chapter quite complete in itself This book will help generate many new research problems and solutions for future mobile multimedia communications. We cannot claim that this book is errorless. Any remarks to improve the text and correct any errors would be highly appreciated.
4,020 citations
TL;DR: A baseband solution for an SDR system and a 2 Mb/s WCDMA design with GSM/GPRS and 802.11b capability that executes all physical layer processing completely in software are discussed.
Abstract: Software-defined radios offer a programmable and dynamically reconfigurable method of reusing hardware to implement the physical layer processing of multiple communications systems. An SDR can dynamically change protocols and update communications systems over the air as a service provider allows. In this article we discuss a baseband solution for an SDR system and describe a 2 Mb/s WCDMA design with GSM/GPRS and 802.11b capability that executes all physical layer processing completely in software. We describe the WCDMA communications protocols with a focus on latency reduction and unique implementation techniques. We also describe the underlying technology that enables software execution. Our solution is programmed in C and executed on a multithreaded processor in real time.
131 citations
18 Jul 2005
TL;DR: This work describes the generation of the simulation environment for the Sandbridge Sandblaster multithreaded processor, and dynamically compile an executing program and processor model to a target platform, providing fast interactive responses with accelerated simulation capability.
Abstract: We describe the generation of the simulation environment for the Sandbridge Sandblaster multithreaded processor. The processor model is described using the Sandblaster architecture Description Language (SaDL), which is implemented as python objects. Specific processor implementations of the simulation environment are generated by calling the python objects. Using just-in-time compiler technology, we dynamically compile an executing program and processor model to a target platform, providing fast interactive responses with accelerated simulation capability. Using this approach, we simulate up to 100 million instructions per second on a 1 GHz Pentium processor. This allows the system programmer to prototype many applications in real-time within the simulation environment, providing a dramatic increase in productivity and allowing flexible hardware-software trade-offs.
20 citations
01 Jan 2003
TL;DR: This research presents a novel and scalable approaches to solve the challenge of integrating 3D image recognition and 3D sensing into the traditional e-commerce system.
Abstract: Daniel Iancu (Sandbridge Technologies Inc., White Plains, NY 10601 USA; diancu@sandbridgetech.com); John Glossner (Sandbridge Technologies Inc. & Delft University of Technology, Computer Engineering, Electrical Engineering Mathematics and Computer Science, Delft, The Netherlands; jglossner@sandbridgetech.com); Vladimir Kotlyar (Sandbridge Technologies Inc., White Plains, NY 10601 USA; vkotlyar@sandbridgetech.com); Hua Ye (Sandbridge Technologies Inc., White Plains, NY 10601 USA; huaye@sandbridgetech.com); Mayan Moudgill (Sandbridge Technologies Inc., White Plains, NY 10601 USA; mayan@sandbridgetech.com); Erdem Hokenek (Sandbridge Technologies Inc., White Plains, NY 10601 USA; ehokenek@sandbridgetech.com);
7 citations
Proceedings Article•
15 Feb 2006TL;DR: In this paper, implementation and analysis of an entire wireless communication system physical layer receiver in software is presented and the two paramount issues, namely real-time performance of the executable, as compared to hardware implementation performance, and the power consumption projections for the DSP executing the receiver code are presented.
Abstract: In this paper, implementation and analysis of an entire wireless communication system physical layer receiver in software is presented. The two paramount issues, namely real-time performance of the executable, as compared to hardware implementation performance, and the power consumption projections for the DSP executing the receiver code are presented. Issues investigated include the paradigm-shift from hardware centric algorithm realizations to a software centric methodology, fixed point DSP algorithm implementation in ANSI C, synchronization of receive and transmit events such as TDMA operations, and processing chain partitioning in a software defined radio baseband processing environment. Results presented will include the MIPS requirements of the processing chain, as well as code and data partitioning trade-offs.
3 citations