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Journal ArticleDOI

Software-programmable digital pre-distortion on new generation FPGAs

01 Mar 2014-Analog Integrated Circuits and Signal Processing (Springer US)-Vol. 78, Iss: 3, pp 573-587
TL;DR: A software programmable design flow that facilitates the implementation and integration of efficient digital pre-distortion (DPD) solutions on the leading-edge field programmable gate arrays, combining industry-standard embedded processors and programmable logic fabric into one chip.
Abstract: In this paper we present a software programmable design flow that facilitates the implementation and integration of efficient digital pre-distortion (DPD) solutions on the leading-edge field programmable gate arrays, combining industry-standard embedded processors and programmable logic fabric into one chip. In addition to software programmability, another key contribution of this design flow is the flexible partitioning of functionality among the hardware and software components, depending on the complexity of the DPD parameter estimation algorithm in use. We have applied processor-specific optimizations to the software implementation and used Vivado high-level synthesis (HLS) tool as the design tool for the programmable logic. Furthermore, we have compared two different techniques for the integration of hardware and software components, where we have chosen the one with better area/latency trade-off. We present a comprehensive study reporting the DPD parameter update times when exploring the partitioning of the functionality among hardware and software. For low-complexity algorithms, we show that a software-only solution is applicable after carrying out the processor-specific software optimizations. For higher-complexity algorithms, we use Vivado HLS to accelerate the time-consuming blocks in the programmable logic, leading to a speed-up factor of up to 7× in the overall algorithm execution time. We present the performance results for two target devices. We also show that our accelerators use only a small portion of the programmable logic fabric on these devices and that a significant reduction of the system's energy consumption can be obtained by leveraging the FPGA fabric.
Citations
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Journal ArticleDOI
TL;DR: It is observed that the TMV model reduces the normalized mean-square error and the adjacent channel error power ratio for the upper adjacent channel (upper ACEPR) by 1.6 dB when it is compared to the previous LV and KV models under the same computational complexity.
Abstract: In this paper, a Takenaka---Malmquist---Volterra (TMV) model structure is employed to improve the approximations in the low-pass equivalent behavioral modeling of radio frequency (RF) power amplifiers (PAs). The Takenaka---Malmquist basis generalizes the orthonormal basis functions previously used in this context. In addition, it allows each nonlinearity order in the expanded Volterra model to be parameterized by multiple complex poles (dynamics). The state-space realizations for the TMV models are introduced. The pole sets for the TMV model and also for the previous Laguerre---Volterra (LV) and Kautz---Volterra (KV) models are obtained using a constrained nonlinear optimization approach. Based on experimental data measured on a GaN HEMT class AB RF PA excited by a WCDMA signal, it is observed that the TMV model reduces the normalized mean-square error and the adjacent channel error power ratio for the upper adjacent channel (upper ACEPR) by 1.6 dB when it is compared to the previous LV and KV models under the same computational complexity.

7 citations


Cites background from "Software-programmable digital pre-d..."

  • ...Therefore, the successful design of a DPD scheme is strongly conditioned by the availability of a high-accurate and low-complexity model for representing the inverse (in the case of both the direct and indirect learning architectures) and also forward (only in the case of the direct learning architecture) RF PA characteristics [1,15,19,21]....

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Proceedings ArticleDOI
03 Dec 2015
TL;DR: This work is the first to integrate dataflow-based power management systematically in the context of adaptive DPD implementation and provides a methodology for dynamic power management under the dataflow paradigm.
Abstract: Dataflow models of computation are widely used for modeling signal processing systems. These models have inherent concurrency and the task (actor) execution depends only on the availability of the input data (tokens). This property of dataflow models can be exploited for dynamic power management by automatically switching off the actors with no available input tokens. This idea is applied in this paper for efficient modeling and implementation of an adaptive Digital Predistortion (DPD) filter. The DPD filter is required to operate with different profiles under varying operation scenarios, hence requiring a methodology to manage power dynamically. The paper presents a dataflow model for Adaptive Digital Predistortion based on the Core Functional Dataflow (CFDF) model of computation using the Light Weight Dataflow (LWDF) programming methodology. The paper also provides a methodology for dynamic power management under the dataflow paradigm. To the authors' best knowledge, this work is the first to integrate dataflow-based power management systematically in the context of adaptive DPD implementation.

5 citations

Proceedings ArticleDOI
03 Dec 2015
TL;DR: This paper focuses on the implementation of this efficient coefficients estimation algorithm based on orthonormal basis functions that achieves the low computational complexity while maintaining the estimation accuracy on a field programmable gate array (FPGA) platform.
Abstract: In modern wireless communication systems, the adaptive digital predistortion (DPD) is widely used to compensate for the nonlinearity in the radio front-end. In the DPD implementation, the conventional coefficient estimation algorithm is computationally intensive and prevents the application of complex DPD models. In [1], we have derived an efficient coefficients estimation algorithm based on orthonormal basis functions that achieves the low computational complexity while maintaining the estimation accuracy. In this paper, we focus on the implementation of this efficient coefficients estimation algorithm on a field programmable gate array (FPGA) platform. Compared with the conventional recursive least squares (RLS) algorithm, the low complexity algorithm can achieve the same linearization performance while saving about 80% hardware resources.

3 citations


Cites methods from "Software-programmable digital pre-d..."

  • ...To facilitate the FPGA implementation and integration of efficient DPD solutions, authors in [9] proposed the software programmable design flow....

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Proceedings ArticleDOI
01 Nov 2015
TL;DR: This paper proposes data- parallel, reconfigurable predistortion and measures its performance on mobile GPUs: Qualcomm Adreno 330 and ARM Mali T628.
Abstract: 3GPP LTE-A offers new technologies such as non-contiguous carrier allocation for improving radio spectrum utilization. However, implementation of these technologies is challenging because of intermodulation distortion caused by non- linearity of components. Digital Predistortion (DPD) offers a way for compensating for these nonlinearities by modifying the digital baseband signal. As most consumer-oriented mobile devices are equipped with powerful Graphics Processing Units (GPUs), it has become possible to implement DPD functionality to such devices with no additional hardware cost. In this paper, we propose data- parallel, reconfigurable predistortion and measure its performance on mobile GPUs: Qualcomm Adreno 330 and ARM Mali T628.

3 citations

Journal ArticleDOI
TL;DR: In this paper , an approach that modifies the Polar Volterra series expanded by a set of Laguerre Orthonormal Basis Functions and the Polar VOLTERRA series using independent truncation techniques to significantly reduce the amount of parameters was proposed.
Abstract: This article proposes an approach that modifies the Polar‐Volterra series expanded by a set of Laguerre Orthonormal Basis Functions and the Polar‐Volterra series using independent truncation techniques to significantly reduce the amount of parameters, where the resulting models reproduce the distortions of the nonlinearities of a radio frequency power amplifier (RF PA). An RF PA GaN HEMT class AB, stimulated by a wave centered at 900 MHz modulated by two 3GPP WCDMA envelope signals, each having a bandwidth of 3.84 MHz and shifted by 5 MHz, was used. A comparison of several models showed that the two proposed models, both containing a larger number of independent truncation factors, can provide a reduction over 50% in the number of generated coefficients, reaching a maximum of 84%. In another comparison with the other models, the modified Polar‐Volterra series expanded by a set of Laguerre functions significantly improved the modeling accuracy, quantified by improvements of normalized mean square error of up to 6.51 dB.

1 citations

References
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Book
31 Jul 2007
TL;DR: In this paper, the authors present a very up-to-date and practical book, written by engineers working closely in 3GPP, gives insight into the newest technologies and standards adopted by threeGPP with detailed explanations of the specific solutions chosen and their implementation in HSPA and LTE.
Abstract: This very up-to-date and practical book, written by engineers working closely in 3GPP, gives insight into the newest technologies and standards adopted by 3GPP, with detailed explanations of the specific solutions chosen and their implementation in HSPA and LTE. The key technologies presented include multi-carrier transmission, advanced single-carrier transmission, advanced receivers, OFDM, MIMO and adaptive antenna solutions, advanced radio resource management and protocols, and different radio network architectures. Their role and use in the context of mobile broadband access in general is explained. Both a high-level overview and more detailed step-by-step explanations of HSPA and LTE implementation are given. An overview of other related systems such as TD SCDMA, CDMA2000, and WIMAX is also provided.This is a 'must-have' resource for engineers and other professionals working with cellular or wireless broadband technologies who need to know how to utilize the new technology to stay ahead of the competition.The authors of the book all work at Ericsson Research and are deeply involved in 3G development and standardisation since the early days of 3G research. They are leading experts in the field and are today still actively contributing to the standardisation of both HSPA and LTE within 3GPP. * Gives the first explanation of the radio access technologies and key international standards for moving to the next stage of 3G evolution: fully operational mobile broadband* Describes the new technologies selected by the 3GPP to realise High Speed Packet Access (HSPA) and Long Term Evolution (LTE) for mobile broadband * Gives both higher-level overviews and detailed explanations of HSPA and LTE as specified by 3GPP

1,554 citations

Journal ArticleDOI
TL;DR: This paper relates the general Volterra representation to the classical Wiener, Hammerstein, Wiener-Hammerstein, and parallel Wiener structures, and describes some state-of-the-art predistortion models based on memory polynomials, and proposes a new generalizedMemory polynomial that achieves the best performance to date.
Abstract: Conventional radio-frequency (RF) power amplifiers operating with wideband signals, such as wideband code-division multiple access (WCDMA) in the Universal Mobile Telecommunications System (UMTS) must be backed off considerably from their peak power level in order to control out-of-band spurious emissions, also known as "spectral regrowth." Adapting these amplifiers to wideband operation therefore entails larger size and higher cost than would otherwise be required for the same power output. An alternative solution, which is gaining widespread popularity, is to employ digital baseband predistortion ahead of the amplifier to compensate for the nonlinearity effects, hence allowing it to run closer to its maximum output power while maintaining low spectral regrowth. Recent improvements to the technique have included memory effects in the predistortion model, which are essential as the bandwidth increases. In this paper, we relate the general Volterra representation to the classical Wiener, Hammerstein, Wiener-Hammerstein, and parallel Wiener structures, and go on to describe some state-of-the-art predistortion models based on memory polynomials. We then propose a new generalized memory polynomial that achieves the best performance to date, as demonstrated herein with experimental results obtained from a testbed using an actual 30-W, 2-GHz power amplifier

1,305 citations

Journal ArticleDOI
TL;DR: An overview of the LTE radio interface, recently approved by the 3GPP, together with a more in-depth description of its features such as spectrum flexibility, multi-antenna transmission, and inter-cell interference control are provided.
Abstract: This article provides an overview of the LTE radio interface, recently approved by the 3GPP, together with a more in-depth description of its features such as spectrum flexibility, multi-antenna transmission, and inter-cell interference control. The performance of LTE and some of its key features is illustrated with simulation results. The article is concluded with an outlook into the future evolution of LTE.

886 citations

Journal ArticleDOI
Jason Cong, Bin Liu, Stephen Neuendorffer1, Juanjo Noguera1, Kees Vissers1, Zhiru Zhang 
TL;DR: AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx are used as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains.
Abstract: Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS msystem-on-chip design complexityethodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.

728 citations