SOP: what is it and why? A new microsystem-integration technology paradigm-Moore's law for system integration of miniaturized convergent systems of the next decade
TL;DR: The SOP package overcomes both the computing limitations and integration limitations of SOC, SIP, MCM, and traditional system packaging by having global wiring as well as RF, digital, and optical component integration in the package, not in the chip.
Abstract: In the past, microsystems packaging played two roles: 1) it provided I/O connections to and from integrated circuits (ICs) or wafer-level packaging (WLP), and 2) it interconnected both active and passive components on system level boards, referred to as systems packaging. Both were accomplished by interconnections or multilayer wiring at the package or board level. More recently, the IC devices have begun to integrate not only more and more transistors, but also active and passive components on an individual chip, leading the community to believe that someday there may be a single-chip complete system, referred to as system-on-chip (SOC). This can be called horizontal or two-dimensional (2-D) integration of IC blocks in a single-chip toward end-product systems. The community began to realize, however, that such an approach presents fundamental, engineering, and investment limits, as well as computing and communication limits for wireless and wired systems over the long run. This led to 3-D packaging approaches, often referred to as system-in-package (SIP). The SIP, while providing major opportunities in both miniaturization and integration for advanced and portable electronic products, is a subsystem, limited by the CMOS process just like the SOC. Some existing and emerging applications, however, include sensors, memory modules and embedded processors with DRAMs. More recent 3-D solutions, which incorporate stacked package approaches, offer solutions toward faster time-to-market and business impediments that have plagued MCM deployment for the past decade. There is a new emerging concept called system-on-package (SOP). With SOP, the package, not the board, is the system. As such, SOP is beginning to address the shortcomings of both SOC and SIP, as well as traditional packaging which is bulky, costly, and lower in performance and reliability than ICs, in two ways: 1) It uses CMOS-based silicon for what it is good for, namely, for transistor integration, and the package, for what it is good for, namely, RF, optical, and digital integration by means of IC-package-system codesign. The SOP package, therefore, overcomes both the computing limitations and integration limitations of SOC, SIP, MCM, and traditional system packaging. It does this by having global wiring as well as RF, digital, and optical component integration in the package, not in the chip. The SOP, therefore, includes both active and passive components in thin-film form, in contrast with indiscrete or thick-film form, including embedded digital, RF, and optical components, and functions in a microminiaturized package or board.
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25 Sep 2006
TL;DR: The historical evolution of power is traced and the impact of power and power density on thermal solution designs is summarized and some of the future trends in demand and solution strategies that are being developed by academic and industrial researchers to meet these demands are discussed.
Abstract: Increasing microprocessor performance has historically been accompanied by increasing power and increasing on-chip power density, both of which present a cooling challenge. In this paper, the historical evolution of power is traced and the impact of power and power density on thermal solution designs is summarized. Industrial and academic researchers have correspondingly increased their focus on elucidating the problem and developing innovative solutions in devices, circuits, architectures, packaging and system level heatsinking. Examples of some of the current packaging and system thermal solutions are provided to illustrate the strategies used in their design. This is followed by a brief discussion of some of the future trends in demand and solution strategies that are being developed by academic and industrial researchers to meet these demands. Potential opportunities and limitations with these strategies are reviewed
323 citations
Cites background from "SOP: what is it and why? A new micr..."
...2) Additionally, there is more interest in microsystems where heterogeneous technology integration at various levels is being actively pursued to enhance performance [15]....
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Book•
01 Jan 2008
TL;DR: In this article, the first book on 3D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits.
Abstract: With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance.
Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck" challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed.
This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits.
* Demonstrates how to overcome "Interconnect Bottleneck" with 3D Integrated Circuit Design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers.
* The FIRST book on 3D Integrated Circuit Design...provides up-to-date information that is otherwise difficult to find;
* Focuses on design issues key to the product development cyle...good design plays a major role in exploiting the implementation flexibilities offered in the third dimension;
* Provides broad coverage of 3D IC Design, including Interconnect Prediction Models, Thermal Management Techniques, and Timing Optimization...offers practical view of designing 3D circuits.
289 citations
TL;DR: The opportunities of pervasive health monitoring through data linkages with other health informatics systems including the mining of health records, clinical trial databases, multiomics data integration, and social media are discussed.
Abstract: Objective: This paper discusses the evolution of pervasive healthcare from its inception for activity recognition using wearable sensors to the future of sensing implant deployment and data processing. Methods: We provide an overview of some of the past milestones and recent developments, categorized into different generations of pervasive sensing applications for health monitoring. This is followed by a review on recent technological advances that have allowed unobtrusive continuous sensing combined with diverse technologies to reshape the clinical workflow for both acute and chronic disease management. We discuss the opportunities of pervasive health monitoring through data linkages with other health informatics systems including the mining of health records, clinical trial databases, multiomics data integration, and social media. Conclusion: Technical advances have supported the evolution of the pervasive health paradigm toward preventative, predictive, personalized, and participatory medicine. Significance: The sensing technologies discussed in this paper and their future evolution will play a key role in realizing the goal of sustainable healthcare systems.
283 citations
Cites methods from "SOP: what is it and why? A new micr..."
...In the case where the sensors and ASIC can only be fabricated using their respect iv optimum technologies, advanced integration processe s known as System-in-Package (SiP) [55, 56] are used to drastically reduce sensing system footprint compared to traditi onal horizontal assembly with PCBs....
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TL;DR: Traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed, including approaches based on the hybrid integration of multiple chips (multi- chip solutions) as wellAs system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques.
Abstract: The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control phys ...
216 citations
TL;DR: In this article, the authors reviewed possible solutions based on decoupling or isolation for suppressing power distribution network (PDN) noise on package or printed circuit board (PCB) levels.
Abstract: Mitigating power distribution network (PDN) noise is one of the main efforts for power integrity (PI) design in high-speed or mixed-signal circuits. Possible solutions, which are based on decoupling or isolation concept, for suppressing PDN noise on package or printed circuit board (PCB) levels are reviewed in this paper. Keeping the PDN impedance very low in a wide frequency range, except at dc, by employing a shunt capacitors, which can be in-chip, package, or PCB levels, is the first priority way for PI design. The decoupling techniques including the planes structure, surface-mounted technology decoupling capacitors, and embedded capacitors will be discussed. The isolation approach that keeps part of the PDN at high impedance is another way to reduce the PDN noise propagation. Besides the typical isolation approaches such as the etched slots and filter, the new isolation concept using electromagnetic bandgap structures will also be discussed.
200 citations
Cites background from "SOP: what is it and why? A new micr..."
...with RF circuits, and higher throughput of data communication [5]....
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References
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01 Jun 2000
TL;DR: Optical interconnects to silicon CMOS chips are discussed in this paper, where various arguments for introducing optical interconnections to silicon chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed.
Abstract: The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedence matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chop global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects.
1,233 citations
"SOP: what is it and why? A new micr..." refers background in this paper
...A potential solution for such problems is the use of embedded optical clock distribution in the package, which is immune to most noise sources [13]–[22]....
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01 Jun 2000
TL;DR: In this article, a fully embedded board-level guided-wave optical interconnection is presented to solve the packaging compatibility problem, where all elements involved in providing high-speed optical communications within one board are demonstrated.
Abstract: A fully embedded board-level guided-wave optical interconnection is presented to solve the packaging compatibility problem. All elements involved in providing high-speed optical communications within one board are demonstrated. Experimental results on a 12-channel linear array of thin-film polyimide waveguides, vertical-cavity surface-emitting lasers (VCSELs) (42 /spl mu/m), and silicon MSM photodetectors (10 /spl mu/m) suitable for a fully embedded implementation are provided. Two types of waveguide couplers, titled gratings and 45/spl deg/ total internal reflection mirrors, are fabricated within the polyimide waveguides. Thirty-five to near 100% coupling efficiencies are experimentally confirmed. By doing so, all the real estate of the PC board surface are occupied by electronics, and therefore one only observes the performance enhancement due to the employment of optical interconnection but does not worry about the interface problem between electronic and optoelectronic components unlike conventional approaches. A high speed 1-48 optical clock signal distribution network for Cray T-90 super computer is demonstrated. A waveguide propagation loss of 0.21 dB/cm at 850 nm was experimentally confirmed for the 1-48 clock signal distribution and for point-to-point interconnects. The feasibility of using polyimide as the interlayer dielectric material to form hybrid three-dimensional interconnects is also demonstrated. Finally, a waveguide bus architecture is presented, which provides a realistic bidirectional broadcasting transmission of optical signals. Such a structure is equivalent to such IEEE standard bus protocols as VME bus and FutureBus.
250 citations
Book•
31 Dec 2003
TL;DR: In this paper, the authors present an overview of the current state of the art in the field of discrete passive components and their application in the context of Capacitor technology and its applications.
Abstract: Contributors.Preface.1 Introduction (Richard K. Ulrich).1.1 Status and Trends in Discrete Passive Components.1.2 Definitions and Configurations of Integrated Passives.1.3 Comparison to Integrated Active Devices.1.4 Substrates and Interconnect Systems for Integrated Passives.1.5 Fabrication of Integrated Passives.1.6 Reasons for Integrating Passive Devices.1.7 Problems with Integrating Passive Devices.1.8 Applications for Integrated Passives.1.9 The Past and Future of Integrated Passives.1.10 Organization of this Book.References.2 Characteristics and Performance of Planar Resistors (Richard K. Ulrich).2.1 Performance Parameters.2.2 Resistance in Electronic Materials.2.3 Sizing Integrated Resistors.2.4 Trimming.References.3 Integrated Resistor Materials and Processes (Richard K. Ulrich).3.1 Single-Component Metals.3.2 Metal Alloys and Metal-Nonmetal Compounds.3.3 Semiconductors.3.4 Cermets.3.5 Polymer Thick Film.3.6 Ink Jet Deposition.3.7 Commercialized Processes.3.8 Summary.References.4 Dielectric Materials for Integrated Capacitors (Richard K. Ulrich).4.1 Polarizability and Capacitance.4.2 Capacitance Density.4.3 Temperature Effects.4.4 Frequency and Voltage Effects.4.5 Aging Effects.4.6 Composition and Morphology Effects.4.7 Leakage and Breakdown.4.8 Dissipation Factor.4.9 Comparison to EIA Dielectric Classifications.4.10 Matching Dielectric Materials to Applications.References.5 Size and Configuration of Integrated Capacitors (Richard K. Ulrich).5.1 Comparison of Integrated and Discrete Areas.5.2 Layout Options.5.3 Tolerance.5.4 Mixed Dielectric Strategies.5.5 CV Product.5.6 Maximum Capacitance Density and Breakdown Voltage.References.6 Processing Integrated Capacitors (Richard K. Ulrich).6.1 Sputtering.6.2 CVD, PECVD and MOCVD.6.3 Anodization.6.4 Sol-Gel and Hydrothermal Ferroelectrics.6.5 Thin- and Thick-Film Polymers.6.6 Thick-Film Dielectrics.6.7 Interlayer Insulation.6.8 Interdigitated Capacitors.6.9 Capacitor Plate Materials.6.10 Trimming Integrated Capacitors.6.11 Commercialized Integrated Capacitor Technologies.6.12 Summary.References.7 Defects and Yield Issues (Richard K. Ulrich).7.1 Causes of Fatal Defects in Integrated Capacitors.7.2 Measurement of Defect Density.7.3 Defect Density and System Yield.7.3.1 Predicting Yield from Defect Density.7.4 Yield Enhancement Techniques for Capacitors.7.5 Conclusions.References.8 Electrical Performance of Integrated Capacitors (Richard K. Ulrich and Leonard W. Schaper).8.1 Modeling Ideal Passives.8.2 Modeling Real Capacitors.8.3 Electrical Performance of Discrete and Integrated Capacitors.8.4 Dissipation Factor of Real Capacitors.8.5 Measurement of Capacitor Properties.8.6 Summary.References.9 Decoupling (Leonard W. Schaper).9.1 Power Distribution.9.2 Decoupling with Discrete Capacitors.9.3 Decoupling with Integrated Capacitors.9.4 Dielectrics and Configurations for Integrated Decoupling.9.5 Integrated Decoupling as an Entry Application.References.10 Integrated Inductors (Geert J. Carchon and Walter De Raedt).10.1 Introduction.10.2 Inductor Behavior and Performance Parameters.10.3 Inductor Performance Prediction.10.4 Integrated Inductor Examples.10.5 Use of Inductors in Circuits: Examples.10.6 Conclusions.Acknowledgments.References.11 Modeling of Integrated Inductors and Resistors for Microwave Applications (Zhenwen Wang, M. Jamal Deen, and A. H. Rahal).11.1 Introduction.11.2 Modeling of Spiral Inductors.11.3 Modeling of Thin-Film Resistors.11.4 Conclusions.References.Appendix: Characteristics of Microscript Lines.12 Other Applications and Integration Technologies (Elizabeth Logan, Geert J. Carchon, Walter De Raedt, Richard K. Ulrich, and Leonard W. Schaper).12.1 Demonstration Devices Fabricated with Integrated Passives.12.2 Commercialized Thin-Film Build-Up Integrated Passives.12.3 Other Integrated Passive Technologies.12.4 Summary.Acknowledgments.References.13 The Economics of Embedded Passives (Peter A. Sandborn).13.1 Introduction.13.2 Modeling Embedded Passive Economics.13.3 Key Aspects of Modeling Embedded Passive Costs.13.4 Example Case Studies.13.5 Summary.Acknowledgments.References.14 The Future of Integrated Passives (Richard K. Ulrich).14.1 Status of Passive Integration.14.2 Issues for Implementation on Organic Substrates.14.3 Progress on Board-Level Implementation.14.4 Three Ways In for Organic Boards.14.5 Conclusion.Index.About the Editors.
213 citations
TL;DR: The authors propose a new system design paradigm, the system on package, which uses electronic product reengineering to meet time-to-market and performance requirements.
Abstract: The authors propose a new system design paradigm, the system on package, which uses electronic product reengineering to meet time-to-market and performance requirements. The system on package promises a higher return on investment than the system on chip.
125 citations
"SOP: what is it and why? A new micr..." refers background in this paper
...SOP goes one step beyond all three of the aforementioned approaches in overcoming both the fundamental and integration shortcomings of SOC, SIP, and MCM, which are limited by CMOS processing and the shortcomings of current packaging for cost, performance, size, and reliability [27]–[30]....
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08 Nov 2004
TL;DR: The system-on-a-package (SOP) concept is considered as the solution of future communication modules, where more functionality, better performance, low cost, and more integrity is needed.
Abstract: The system-on-a-package (SOP) concept is considered as the solution of future communication modules, where more functionality, better performance, low cost, and more integrity is needed. We demonstrate how SOP technology can address the integration platform for future communication systems, especially gigabit wireless communications. After the introduction of the SOP concept, we introduce the critical design building blocks which are required in a viable SOP technology: integrated passives, embedded RF functions, including high-performance filters and baluns, and integrated antenna technologies. Second, we review how the three-dimensional deployment of core elements, such as baluns, lumped inductors, capacitors, and resistors, as well as IF or low-pass filters, enables RF-SOP module development. We demonstrate how advanced radio architectures, including direct conversion, antenna diversity, and collaborative signal processing, are enabled using the SOP technology format. Various ceramic and organic material based multilayer packaging technologies have been used for building such integrated modules as well as circuit blocks. The critical issues and challenges for developing advanced communication platforms using the SOP approach are discussed.
84 citations
"SOP: what is it and why? A new micr..." refers background in this paper
...As IC integration moves to nanoscale and wiring resistance increases, the global wiring delay in SOC becomes too high for computing applications [31]....
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...The most concentrated effort is still at the Georgia Institute of Technology; that is where TABLE I COMPANIES INVOLVED IN SOP-RELATED PRODUCT TECHNOLOGIES [31], [32]...
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