Speeding up an integer-N PLL by controlling the loop filter charge
22 Jul 2003-IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing (IEEE)-Vol. 50, Iss: 7, pp 343-354
TL;DR: This paper studies a group of methods designed to speed-up the frequency step response of integer-N phase-locked loops (PLLs) and introduces a considerably simpler waveform based on the use of two current pulses.
Abstract: This paper studies a group of methods designed to speed-up the frequency step response of integer-N phase-locked loops (PLLs). The methods are based on current signals connected to the loop filter. Optimal speed-up waveforms are found mathematically using a linear PLL model. The paper also discusses problems associated with this theoretical waveform and introduces a considerably simpler waveform based on the use of two current pulses. This method uses excess output frequency to quickly cancel the accumulated phase error. In order to accelerate the decay of the phase error, the PLL is first overdriven at the beginning of the frequency transition with an external charge pulse to the loop filter. As the phase error goes rapidly to zero, the frequency error is also reduced to zero by another charge pulse. The theory presented here is verified by measurements using a practical RF synthesizer.
Citations
More filters
TL;DR: A phase-locked loop algorithm appropriated for digital-signal-processor-based control implementations, where the operation of a static-power converter needs to be synchronized with an ac network, is presented.
Abstract: In this paper, a phase-locked loop algorithm appropriated for digital-signal-processor-based control implementations, where the operation of a static-power converter needs to be synchronized with an ac network, is presented. The proposed algorithm includes a multiplier, a filter, a feedback closed loop, and a numerically controlled oscillator stage. As a result, a discrete sine (and cosine) signal is generated in synchronism with the fundamental component of an external-reference (ER) signal. Moreover, the sampling period of the algorithm is adjusted at each sampling instant such that an integer number of sampling periods per period of the ER signal is ensured. This is the main feature, and it is achieved by using a discrete rectangular window filter and a discrete controller. The proposed algorithm code is simple, stable, and presents high noise rejection. A comprehensive theoretical justification and various rigorous experimental tests are included.
122 citations
TL;DR: A ldquoflying-adderrdquo architecture based PLL (FAPLL) is constructed, which is instantiated multiple times in this SoC for different functions, resulting in significant chip cost reduction.
Abstract: The spirit of system-on-chip (SoC) approach is to integrate more and more system functions into one single chip. Consequently, the on-chip clock requirement could be very complicated due to the various functions the chip has to support. To fulfill those clock needs, it is not uncommon for more than several phase-locked loop (PLLs) to be used within one such large chip. Designing these on-chip PLLs is a very challenging task in term of cost and performance. To solve this problem for a HDTV SoC of over 50 millions transistors, a ldquoflying-adderrdquo architecture based PLL (FAPLL) is constructed. This generic FAPLL is instantiated multiple times in this SoC for different functions, resulting in significant chip cost reduction.
33 citations
Cites methods from "Speeding up an integer-N PLL by con..."
...During the design process of this large SoC, investigation has been done on integer- , fractional- PLL and all-digital PLL (ADPLL) architectures [1]–[3]....
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24 Oct 2005
TL;DR: Design of bandwidth adaptive phase-locked loops (PLL) to achieve fast locking is presented and the measured results show that the experimental chip has properties of fast locking less than 4 mus and low power consumption about 18mW.
Abstract: Design of bandwidth adaptive phase-locked loops (PLL) to achieve fast locking is presented in this paper. The proposed topology uses only one adaptive phase frequency detector (PFD) and controllable charge pumps to realize adaptive bandwidth scheme. With a SMIC standard 0.25mum 1P5M 2.5V CMOS logic process, the measured results show that the experimental chip has properties of fast locking less than 4 mus and low power consumption about 18mW
12 citations
Cites methods from "Speeding up an integer-N PLL by con..."
...The scheme of adaptive bandwidth is proposed recently to satisfy the design tradeoff including dynamic gain adjustment of VCO [1], adaptive controlling of frequency divider [2] and charge current dynamic adjustment [3] which is the method adopted mostly because of the features of easy implement and good stability....
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TL;DR: A digital-control adaptive phase-locked loop with a digital locking-in monitor (LIM) consisting of a time-to-digital converter (TDC) and a bandwidth control unit (BCU) is proposed to reduce the locking time as well as to suppress the jitter when locked.
Abstract: In this brief, a digital-control adaptive phase-locked loop (PLL) with a digital locking-in monitor (LIM) consisting of a time-to-digital converter (TDC) and a bandwidth control unit (BCU) is proposed to reduce the locking time as well as to suppress the jitter when locked. It uses a delay-independent threshold in a dual-slope transfer function to detect the locked state according to the counting result of the proposed TDC, which feeds to the BCU to switch the bandwidth of PLL. Then the PLL is switched from a wide loop bandwidth (6 MHz) to a narrow bandwidth (3 MHz) in the locked state. To verify the proposed scheme, the proposed adaptive PLL is implemented in a TSMC 0.18 μm 1P6M CMOS process with a supply voltage of 1.8 V. The measurement results show that the locking time is reduced by 67% while with a RMS jitter of only 8.79 ps when operating at 1.6 GHz.
11 citations
01 Jan 2013
TL;DR: A general approach for analytical calculation of phase detector characteristic for classical phase-locked loop for various signal waveforms is proposed, thereby significantly reducing time required for numerical simulation of PLL.
Abstract: Yuldashev, Renat Synthesis of Phase-Locked Loop: analytical methods and simulation Jyväskylä: University of Jyväskylä, 2013, 50 p.(+included articles) (Jyväskylä Studies in Computing ISSN 1456-5390; 175) ISBN 978-951-39-5487-1 (nid.) ISBN 978-951-39-5490-1 (PDF) Finnish summary Diss. One of the main approaches for PLL analysis is the numerical simulation of the models on the level of electronic realization. It is a challenging task, because the frequency of oscillators in modern computers and communication systems can reach up to several gigahertz. However, the frequency of the loop bandwidth may be only multiple of kilohertz. This 3 to 6 order of magnitude difference in frequencies makes simulation of PLL very difficult. To overcome these difficulties, a special mathematical model of phase-locked loop, in which only slow time scale of signals phases and frequencies is considered. That, in turn, requires to construct mathematical model of all components of the PLL. One of the main components of the PLL is a phase detector, whose operation depends on the waveforms of considered signals. In this work a general approach for analytical calculation of phase detector characteristic for classical phase-locked loop for various signal waveforms is proposed. Obtained PLL and PLL with a squarer models allow to use phase-frequency model for PLL, thereby significantly reducing time required for numerical simulation.
5 citations
Cites background from "Speeding up an integer-N PLL by con..."
...…by researchers and engineers in Finland (see e.g. (Kauraniemi and Vuori, 1997; Vankka, 1997; Kauraniemi and Vuori, 1997; Ahola et al., 1998, 1999; Hakkinen and Kostamovaara, 2003; Ahola and Halonen, 2003; Aaltonen et al., 2005; Rapinoja et al., 2006; Saukoski et al., 2008; von Lerber et al.,…...
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References
More filters
Book•
30 Jun 1994
TL;DR: Building Blocks for Frequency Synthesis Using Phase-Locked Loops using Sampled-Data Control Systems and Fast-Switching Frequency Synthesizer Design Considerations.
Abstract: Building Blocks for Frequency Synthesis Using Phase-Locked Loops. Phase Noise and Its Impact Upon System Performance. Phase-Locked Loop Analysis for Continuous Linear Systems. Frequency Synthesis Using Sampled-Data Control Systems. Fast-Switching Frequency Synthesizer Design Considerations. Hybrid Phase-Locked Loops. MACSET -- A Computer Program for the Design and Analysis of Phase-Locked Loop Frequency Synthesizers. Fractional-N Frequency Synthesis.
148 citations
TL;DR: In this article, a 900 MHz phase-locked loop frequency synthesizer implemented in a 0.6/spl mu/m CMOS technology is developed for the wireless integrated network sensors applications.
Abstract: A 900-MHz phase-locked loop frequency synthesizer implemented in a 0.6-/spl mu/m CMOS technology is developed for the wireless integrated network sensors applications. It incorporates an automatic switched-capacitor (SC) discrete-tuning loop to extend the overall frequency tuning range to 20%, while the VCO gain (K/sub VCO/) resulting from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V in order to improve the reference spurs and noise performance. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset frequency and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3-V supply.
144 citations
05 May 1997
TL;DR: The challenges in the design of frequency synthesizers used in wireless transceivers are described and a number of synthesizer architectures are presented along with their merits and drawbacks.
Abstract: This paper describes the challenges in the design of frequency synthesizers used in wireless transceivers. Following a review of design issues and the effect of nonidealities, we present a number of synthesizer architectures along with their merits and drawbacks. We also describe the difficulties in the design of some of the building blocks and consider the role of synthesizers in emerging applications.
130 citations
"Speeding up an integer-N PLL by con..." refers background in this paper
...Depending on the telecommunication system the frequency step requirements of the synthesizer can vary from milliseconds to micro seconds [1] and spur attenuation typically between 60‐70 dBc [ 2 ]....
[...]
TL;DR: In this article, an adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described, which combines contradictory requirements posed by different performance aspects such as settling time, phase noise, and spurious signals.
Abstract: An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architecture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs continuously, without switching of loop filter components, and without interaction from outside of the tuning system. The relationship of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented, and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL, optimized for use in a multiband (global) car-radio tuner IC, is described in detail. The realized tuning system achieved state-of-the-art settling time and spectral purity performance in its class (integer-N PLLs): a signal-to-noise ratio of 65 dB, a 100-kHz spurious reference breakthrough signal under -81 dBc, and a residual settling error of 3 kHz after 1 ms, for a 20-MHz frequency step. It simultaneously fulfills the speed requirements for inaudible frequency hopping and the heavy signal-to-noise ratio specification of 64 dB.
110 citations
TL;DR: In this article, a phase-locked loop frequency synthesizer with a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed.
Abstract: A new architecture for phase-locked loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5-/spl mu/m CMOS process, a fully integrated fractional-N synthesizer prototype with a third-order sigma-delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is, 0.9 /spl times/ 1.1 mm/sup 2/. The settling time is less than 100 /spl mu/s and the phase noise is -118 dBc/Hz at 600-kHz offset.
68 citations