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Proceedings ArticleDOI

SPIRIT: a highly robust combinational test generation algorithm

TL;DR: A robust test generation algorithm for combinational circuits based on the Boolean satisfiability method called SPIRIT is presented, which achieves 100% fault efficiency for a full scan version of the ITC'99 benchmark circuits in a reasonable amount of time.
Abstract: In this paper we present a robust test generation algorithm for combinational circuits based on the Boolean satisfiability method called SPIRIT. We elaborate some well-known techniques as well as presenting new techniques that improve the performance and robustness of test generation algorithms. As a result, SPIRIT achieves 100% fault efficiency for a full scan version of the ITC'99 benchmark circuits in a reasonable amount of time.
Citations
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Proceedings ArticleDOI
01 May 2005
TL;DR: Three resistive bridging fault models valid for different CMOS technologies, based on Shockley equations, Berkeley predictive technology model and BSIM4, are presented, accurately describing non-trivial electrical behavior in that technologies.
Abstract: We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) and a technology-specific part. The first model is based on Shockley equations and is valid for conventional but not deep submicron CMOS. The second model is obtained by fitting SPICE data. The third resistive bridging fault model uses Berkeley predictive technology model and BSIM4; it is valid for CMOS technologies with feature sizes of 90nm and below, accurately describing non-trivial electrical behavior in that technologies. Experimental results for ISCAS circuits show that the test patterns obtained for the Shockley model are still valid for the fitted model, but lead to coverage loss under the predictive model.

49 citations


Cites background from "SPIRIT: a highly robust combination..."

  • ...Note that, although the number of RBF test vectors is typically higher than the number of stuck-at test vectors generated by state-of-the-art ATPG systems [22, 23], the number of considered faults is also larger....

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Proceedings ArticleDOI
01 Oct 2006
TL;DR: This work describes a new diagnostic ATPG implementation that uses a generalized fault model and shows that diagnostic resolution can be significantly enhanced over a traditional diagnostic test set aimed only at stuck-at faults.
Abstract: It is now generally accepted that the stuck-at fault model is no longer sufficient for many manufacturing test activities. Consequently, diagnostic test pattern generation based solely on distinguishing stuck-at faults is unlikely to achieve the resolution required for emerging fault types. In this work we describe a new diagnostic ATPG implementation that uses a generalized fault model. It can be easily used in any diagnosis framework to refine diagnostic resolution for complex defects. For various types of faults that include, for example, bridge, transition, and transistor stuck-open, we show that diagnostic resolution can be significantly enhanced over a traditional diagnostic test set aimed only at stuck-at faults. Finally, we illustrate the use of our diagnostic ATPG to distinguish faults derived from a state-of-the-art diagnosis flow based on layout.

48 citations


Cites methods from "SPIRIT: a highly robust combination..."

  • ...[15] E. Gizdarski and H. Fujiwara, “SPIRIT: A Highly Robust Combinational Test Generation Algorithm,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 12, pp. 1446 – 1458, Dec. 2002....

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  • ...Further efficiency was gained through incorporation of structural ATPG heuristics in TEGUS [14] and SPIRIT [15]....

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Journal ArticleDOI
TL;DR: A new data structure for the complete implication graph that increases the precision of implication process is proposed and an efficient test pattern generation algorithm for combinational circuits based on the Boolean satisfiability method (SAT) is presented.
Abstract: In this paper, an efficient test pattern generation (TPG) algorithm for combinational circuits based on the Boolean satisfiability method (SAT) is presented. The authors propose a new data structure for the complete implication graph that increases the precision of implication process. Next, they examine approaches like a single-cone processing, single path-oriented propagation, and backward justification and show that they are efficient to improve robustness of TPG algorithms. Finally, the authors propose efficient techniques and heuristics for these approaches. The resultant automatic test pattern generation system, called SPIRIT (Satisfiability Problem Implementation for Redundancy Identification and Test generation), combines the flexibility of the SAT-based TPG algorithms with the efficiency of the structural TPG algorithms. Experimental results demonstrate the robustness of the proposed TPG algorithm. Without fault simulation, SPIRIT is able to achieve 100% fault efficiency for a large set of benchmark circuits in a reasonable amount of time.

43 citations


Cites methods from "SPIRIT: a highly robust combination..."

  • ...The proposed techniques and heuristics were implemented in SPIRIT [32], [35] and we ran experiments on a 1-GHz Pentium-III PC....

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Journal ArticleDOI
TL;DR: It is demonstrated how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches to efficient utilization of the inherent parallelism of multi-core architectures.
Abstract: Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.

40 citations


Cites background from "SPIRIT: a highly robust combination..."

  • ...Traditional deterministic automatic test pattern generation (ATPG) algorithms work directly on the circuit structure [1–4], possibly in conjunction with additional data structures such as implication graphs [5] or advanced techniques to prune the solution space [6, 7]....

    [...]

Proceedings ArticleDOI
05 Jan 2009
TL;DR: The automatic test pattern generator TIGUAN is presented based on a thread-parallel SAT solver which supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck- at faults which allows to generate patterns for non-standard fault models.
Abstract: We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models.

38 citations


Cites background from "SPIRIT: a highly robust combination..."

  • ...Traditional deterministic automatic test pattern generation (ATPG) algorithms work directly on the circuit structure [1–4], possibly in conjunction with additional data structures such as implication graphs [5] or advanced techniques to prune the solution space [6, 7]....

    [...]

References
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Journal ArticleDOI
Goel1
TL;DR: PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits that uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems and is significantly more efficient than DALG over the general spectrum of combinational Logic circuits.
Abstract: The D-algorithm (DALG) is shown to be ineffective for the class of combinational logic circuits that is used to implement error correction and translation (ECAT) functions. PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits. PODEM uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems. It is shown that PODEM is very efficient for ECAT circuits and is significantly more efficient than DALG over the general spectrum of combinational logic circuits. A distinctive feature of PODEM is its simplicity when compared to the D-algorithm. PODEM is a complete algorithm in that it will generate a test if one exists. Heuristics are used to achieve an efficient implicit search of the space of all possible primary input patterns until either a test is found or the space is exhausted.

1,112 citations

Journal ArticleDOI
Fujiwara1, Shimono
TL;DR: The FAN (fan-out-oriented test generation algorithm) is presented, which is faster and more efficient than the PODEM algorithm reported by Goel and an automatic test generation system composed of the FAN algorithm and the concurrent fault simulation.
Abstract: In order to accelerate an algorithm for test generation, it is necessary to reduce the number of backtracks in the algorithm and to shorten the process time between backtracks. In this paper, we consider several techniques to accelerate test generation and present a new test generation algorithm called FAN (fan-out-oriented test generation algorithm). It is shown that the FAN algorithm is faster and more efficient than the PODEM algorithm reported by Goel. We also present an automatic test generation system composed of the FAN algorithm and the concurrent fault simulation. Experimental results on large combinational circuits of up to 3000 gates demonstrate that the system performs test generation very fast and effectively.

821 citations

Journal ArticleDOI
T. Larrabee1
TL;DR: The author describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits, which allows for the addition of heuristics used by structural search methods, and has produced excellent results on popular test pattern generation benchmarks.
Abstract: The author describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: first, it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits, and second, it applies a Boolean satisfiability algorithm to the resulting formula. This approach differs from previous methods now in use, which search the circuit structure directly instead of constructing a formula from it. The new method is general and effective. It allows for the addition of heuristics used by structural search methods, and it has produced excellent results on popular test pattern generation benchmarks. >

704 citations

Proceedings Article
01 Jan 1987
TL;DR: SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures.
Abstract: An automatic test pattern generation system, SOCRATES, is presented. SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits. Based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures are described. The application of these techniques leads to a considerable reduction of the number of backtrackings and an earlier recognition of conflicts and redundancies. Several experiments using a set of combinational benchmark circuits demonstrate the efficiency of SOCRATES and its cost-effectiveness, even in a workstation environment. >

542 citations

Journal ArticleDOI
TL;DR: SOCRATES as discussed by the authors is an automatic test pattern generation system for combinational and scan-based circuits based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures.
Abstract: An automatic test pattern generation system, SOCRATES, is presented. SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits. Based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures are described. The application of these techniques leads to a considerable reduction of the number of backtrackings and an earlier recognition of conflicts and redundancies. Several experiments using a set of combinational benchmark circuits demonstrate the efficiency of SOCRATES and its cost-effectiveness, even in a workstation environment. >

517 citations