IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 9, SEPTEMBER 2010 1809
Spur Reduction Techniques for Phase-Locked Loops
Exploiting A Sub-Sampling Phase Detector
Xiang Gao, Student Member, IEEE, Eric A. M. Klumperink, Senior Member, IEEE, Gerard Socci, Member, IEEE,
Mounir Bohsali, Member, IEEE, and Bram Nauta, Fellow, IEEE
Abstract—This paper presents phase-locked loop (PLL) refer-
ence-spur reduction design techniques exploiting a sub-sampling
phase detector (SSPD) (which is also referred to as a sampling
phase detector). The VCO is sampled by the reference clock
without using a frequency divider and an amplitude controlled
charge pump is used which is inherently insensitive to mismatch.
The main remaining source of the VCO reference spur is the
periodic disturbance of the VCO by the sampling at the reference
frequency. The underlying VCO sampling spur mechanisms are
analyzed and their effect is minimized by using dummy samplers
and isolation buffers. A duty-cycle-controlled reference buffer and
delay-locked loop (DLL) tuning are proposed to further reduce
the worst case spur level. To demonstrate the effectiveness of the
proposed spur reduction techniques, a 2.21 GHz PLL is designed
and fabricated in 0.18
m CMOS technology. While using a high
loop-bandwidth-to-reference-frequency ratio of 1/20, the reference
spur measured from 20 chips is
80 dBc. The PLL consumes
3.8 mW while the in-band phase noise is
121 dBc/Hz at 200 kHz
and the output jitter integrated from 10 kHz to 100 MHz is
0.3 ps
rms
.
Index Terms—Clock generation, clock multiplier, clocks, fre-
quency multiplication, frequency synthesizer, low jitter, low phase
noise, low power, low spur, phase detector, phase-locked loop
(PLL), sampling phase detector, sub-sampling phase detector.
I. INTRODUCTION
A
CLOCK with high spectral purity is required in many
applications, e.g., in wireless communication systems
to up-convert and down-convert the wanted signals and in
analog-to-digital converters (ADCs) to accurately define the
sampling moments. The spectral purity of the clock source is
critical for the overall system performance. In addition to low
phase noise, the clock source is often also required to have low
spurious tones since clock spurs cause reciprocal mixing of the
neighbor channels to the passband of the IF filter [1] or translate
to deterministic jitter and degrade the ADC signal-to-noise
ratio.
Phase-locked loops (PLLs) are widely used to generate
high-accuracy clocks on chip. In conventional charge pump
(CP) PLLs, the mismatch between the CP up-current source
Manuscript received November 26, 2009; revised May 5, 2010; accepted May
18, 2010. Date of current version August 25, 2010. This paper was approved by
Associate Editor Darrin Young.
X. Gao, E. A. M. Klumperink, and B. Nauta are with the IC-Design
group, University of Twente, 7500 AE Enschede, The Netherlands (e-mail:
gaoxiangemail@gmail.com).
G. Socci and M. Bohsali are with National Semiconductor, Santa Clara, CA
95051 USA.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2010.2053094
Fig. 1. Generic sub-sampling PLL (SSPLL) architecture.
and down-current source is the major source for the reference
spur at the voltage-controlled oscillator (VCO) output [2]–[8].
Mismatches in the CP current sources generate CP output-cur-
rent ripple which is then converted to ripple on the VCO control
voltage by the loop filter (LF), resulting in VCO spurs. A small
filter bandwidth can be used to suppress the ripple, thereby
reducing the VCO spur level. However, most PLL applications
prefer a large bandwidth as it offers fast settling time, reduces
on-chip filter area and reduces the sensitivity of the VCO to
pulling [6]. In order to alleviate the tradeoff between low spur
and large bandwidth, various design techniques have been
proposed to reduce the CP ripple. Examples are CP designs
that improve current source matching [2], [8], detect the cur-
rent source mismatch and then apply analog [4] or digital [5]
calibration, or designs that add a sample-and-hold between the
CP and the loop filter [6], [7]. In this paper, we propose to use a
sub-sampling PLL (SSPLL) architecture [9] and an amplitude
controlled mismatch insensitive CP, which achieves a low refer-
ence spur
80 dBc while using a high bandwidth of .
The design with some measurements has been presented in
[10]. Here we analyze the underlying spur mechanisms, discuss
and analyze circuit operation in more detail and demonstrate
more experimental proof of the concept.
The generic architecture of a SSPLL is shown in Fig. 1. A
sub-sampling phase detector (SSPD) samples the VCO output
with a reference clock Ref and converts the VCO phase error
into sampled voltage variations. A CP converts sampled voltage
to current and injects it to the loop filter. An auxiliary frequency-
locked loop (FLL) guarantees correct frequency locking. The
sub-sampling PD is not a recent invention, but has been used
for a long time in various designs [11]–[16] under the name
“sampling PD”. The contribution of our work, as previously de-
scribed in [9], is the development of techniques which allow a
fully integrated CMOS PLL that exploits the sampling PD to
achieve very low in-band phase noise. In [9] we demonstrated
0018-9200/$26.00 © 2010 IEEE
1810 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 9, SEPTEMBER 2010
Fig. 2. (a) Three-state PFD and timing controlled CP. (b) Conventional low-ripple CP implementation.
that this integrated version of a sampling-based PLL has a great
noise advantage over a classical PLL, especially when the fre-
quency division ratio
is large, i.e., when a high-frequency
VCO is sub-sampled by a low-frequency Ref. In order to em-
phasize this fact, we prefer to use the name “sub-sampling” in
our work. Note that the noise benefit comes from the high detec-
tion gain of a SSPD/CP, due to the high slew-rate of the VCO.
On the other hand, a very high SSPD/CP gain makes full inte-
gration difficult (i.e., limited loop filter capacitance). Therefore,
[9] used a pulsed CP to lower the gain. Unlike a conventional CP,
the on-time of this pulsed CP does not depend on the phase-dif-
ference, but is constant. The phase information is in the sampled
voltage and the function of the CP is (time-windowed) voltage
to current conversion. We will show in Section II-B of this paper
that this CP is inherently insensitive to mismatch, due to its am-
plitude controlled nature. The CP design can thus be largely sim-
plified while still producing small ripple. Although the SSPD
and the amplitude controlled CP have already been used in [9],
they did not lead to a low spur level there. We will show that
this is because the SSPD periodically disturbs the VCO oper-
ation during sampling, causing actually large VCO spurs. The
VCO sampling spur mechanisms will be analyzed in Section III
and design techniques will be proposed to mitigate them. Dif-
ferent from the CP, the SSPD disturbs the VCO without going
through the LF and hence there is no tradeoff between low SSPD
spur and large PLL bandwidth. As a result, very low reference
spur can be achieved while using a high PLL bandwidth. In ad-
dition to low reference spur, the proposed design also achieves
low in-band phase noise and jitter with low power because the
divider noise is eliminated and the SSPD and CP noise is not
multiplied by
in a SSPLL [9]. Circuit implementation con-
sideration will be presented in Section IV. Section V presents
the experimental results andSection VI gives conclusions.
II. S
PUR DUE TO
CHARGE PUMP
We will now first discuss the conventional CP and then the
amplitude-controlled CP for the SSPLL, to explain why the
latter is beneficial in terms of output current ripple generation.
A. Conventional CP
In PLL designs, the phase frequency detector (PFD) and CP
as shown in Fig. 2(a) is often used. During operation, the PFD
compares the phase of the divided-down VCO to the phase of
Ref and generates two signals UP and DN to control the CP.
It converts the VCO phase error into the on-time difference
between the CP up-current source and down-cur-
rent source
. In this conventional CP, and have
a variable on-time but a constant amplitude fixed by biasing.
When the PLL is phase locked, the net charge provided by the
CP should be zero. To maintain the steady-state locking condi-
tion, the following equation must be satisfied:
(1)
In case there is mismatch between the amplitudes of
and
,wehave and . One of the CP
current sources thus has to be on for a longer time in order to
satisfy (1). This causes CP output current ripple as shown in
Fig. 2(a), which is then converted to ripple on the VCO control
voltage by the LF. If
is the amplitude of the fundamental
component of the CP output current ripple, the corresponding
VCO reference spur
can be calculated as [1]
(2)
GAO et al.: SPUR REDUCTION TECHNIQUES FOR PHASE-LOCKED LOOPS EXPLOITING A SUB-SAMPLING PHASE DETECTOR 1811
Fig. 3. (a) SSPD and amplitude-controlled CP. (b) Proposed low-ripple CP implementation.
where is the LF transimpedance transfer function and
is the VCO analog tuning gain in rad/V. When the often-
used second-order RC filter as in Fig. 2(b) is used, we have
(3)
where
and
are the LF zero and pole frequencies.
In most designs, we have
and .
The VCO spur can then be approximated using (2) and (3) as
(4)
Defining a CP feedback gain
as the gain from the VCO
output to the CP output [9], the PLL open loop bandwidth
can be expressed as
(5)
Substituting (5) into (4) yields
(6)
Therefore to reduce the CP-induced VCO spur, we can:
1) adopt a small
, but it is often limited by the phase
margin requirement; 2) use a large
or in other words use
a small
for a given , but it increases filter
capacitor area or reduces VCO analog tuning range; 3) reduce
the CP output current ripple
; 4) use a small loop-band-
width-to-reference-frequency ratio
to have more
ripple suppression. For a given
, there is thus a tradeoff
between low VCO spur and large
. For a given spur re-
quirement, a CP design with lower ripple enables the use of a
higher
, which is often desired as it offers faster settling
time, and reduces on-chip loop filter area and sensitivity of the
VCO to pulling. Fig. 2(b) shows a classical implementation
of a low-ripple CP [8]. The current sources are implemented
with cascoded transistors to boost the output impedance and
improve matching. Another factor which also contributes to
CP current ripple is the charge sharing between the parasitic
capacitances at the current sources’ drain nodes d1 and d2 and
the LF capacitors if their voltages are not equal when they
are connected during CP switching. The conventional CP in
Fig. 2(b) uses a current-steering topology, where
and
are either connected to LF or dumped to . An operational
amplifier acting as unity gain buffer sets
. In this
way,
and are kept on all the time and the voltages
on d1 and d2 are kept constant during CP switching, thereby
minimizing the LF-CP charge sharing
B. Low Spur CP Using Sub-Sampling
Fig. 3(a) shows the top-level schematic of the SSPD/CP
[9]. During operation, the SSPD directly samples the high-fre-
quency VCO with the low-frequency Ref without using a
frequency divider. It detects the phase difference between the
1812 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 9, SEPTEMBER 2010
Fig. 4. (a) Simple model for VCO sampling. (b) VCO sampling with dummy sampler.
VCO and the Ref sampling edge and converts it into a sampled
voltage difference
, which is then used to
control the amplitude of
and . A block Pulser generates
a pulse Pul, non-overlapping with Ref, and switches on/off
and simultaneously. This Pulser controls the CP gain
and also functions as the slave track-and-hold for the VCO
sampling. Therefore, in this CP,
and have variable
amplitudes but a constant on-time equal to the on-time of the
Pulser output
. Assuming ideal switching, the following
equation must be satisfied to meet the steady-state locking
condition of zero net CP output charge:
(7)
In other words,
and must have equal amplitude and
the
and mismatch is eliminated in this CP.
1
Actu-
ally, there is always mismatch between
and if they
are implemented with MOS transistors. However, the SSPLL
loop tunes
and until the amplitudes of and
match, by shifting the sampling/locking point away from
the ideal point (VCO zero-crossing); see Fig. 3(a). So the mis-
match between the current sources’ transistors still causes static
phase error as in a conventional CP, but here it does not generate
CP output current ripple.
Fig. 3(b) shows the proposed low-ripple CP design which is
much simpler than the conventional one in Fig. 2(b). Since
and mismatch will be tuned out by the PLL loop, the current
sources’ output impedance is not an issue and single transistors
are used, which saves voltage headroom. While the conventional
1
This assumes ideal current source switches. In practice, there is also mis-
match between the switches. Due to the finite rise and fall time of Pul, this
causes mismatch in
I
and
I
switch-on time and thus mismatch in
I
and
I
amplitudes. If this is the limiting factor for VCO spur, the Pulser and
the two switches which acts as the slave track and hold for VCO sampling can
be removed and instead a second switch-capacitor circuit can be added to the
SSPD. The CP is then always connected to the LF and no switching is needed.
However, we will see that the CP is not anymore the major spur source in this
SSPLL. It is therefore still beneficial to keep the Pulser as it simplifies the SSPD
design and can be used to control the CP gain [9].
CP needs a unity-gain buffer to keep and mini-
mize CP-LF charge sharing, we discovered that here this can be
achieved by just connecting an extra capacitor
to the cur-
rent dumping node as explained below. In steady state, the net
charge into the LF and
should be both zero. Since
and have equal on-time in both ’connected to LF’ and ’con-
nected to
’ cases, they must also have equal amplitude
in both cases. This condition is met only when
where the finite current source output impedance is actually the
equalizing mechanism. When the drain nodes of the pMOS cur-
rent source
and nMOS current source are connected
together, there is only one drain node voltage satisfying
due to the finite current-source output impedance.
III. S
PUR DUE TO VCO SAMPLING AND
TECHNIQUES TO REDUCE IT
In the previous section, we have shown that the amplitude-
controlled CP in the SSPLL is inherently insensitive to mis-
match and produces small ripple. In the design of [9], a CP
based on the same principle was used. However, a rather poor
46 dBc reference spur was measured. Research shows that this
is because the SSPD disturbs the VCO operation, via periodi-
cally changing the VCO capacitive load, charge injection from
the sampling switch to the VCO and charge sharing between
the VCO tank and the sampling capacitor. In the sub-sections
below, we will analyze these VCO sampling spur mechanisms
and propose techniques to suppress them. We will use a sim-
plified diagram as shown in Fig. 4(a), where an ideal LC tank is
directly sampled by Ref via a switch-and-capacitor SSPD. In the
real design, a buffer will be added between the VCO and SSPD
for isolation. To simplify the analysis and gain insights, we will
firstly ignore the buffer and discuss the effect of the buffer later.
A. BFSK Effect
For an ideal sampler, the sampling clock should be a Dirac
pulse with an infinitesimal duration time. As this requires an un-
practical virtually zero duty cycle clock, a practical sampler is
GAO et al.: SPUR REDUCTION TECHNIQUES FOR PHASE-LOCKED LOOPS EXPLOITING A SUB-SAMPLING PHASE DETECTOR 1813
Fig. 5. (a) Schematic and timing diagram of inverter buffer, where
V
is the inverter switching point voltage. (b) Measured spur variations while tuning the
position of Ref tracking edge via tuning
V
from the design in [9].
usually implemented using a track-and-hold driven by a block-
waveform with more practical duty-cycle as in Fig. 4(a). When
Ref turns on the switch, the sampling capacitor
is con-
nected to the VCO and becomes part of the VCO loading. When
Ref turns off the switch,
is disconnected and the VCO is
not loaded by
. Therefore, the periodic switching of the
sampler at frequency
modulates in a way similar to
the case of binary frequency shift keying (BFSK) as shown in
Fig. 4(a). Assuming
, the resulting VCO refer-
ence spur can be calculated as (see the Appendix)
(8)
where
is the Ref duty cycle. When there is a buffer between
the VCO and SSPD as in [9],
in (8) should be replaced by
the effective capacitance change seen by the VCO due to Ref
switching.
Equation (8) indicates that the BFSK effect induced refer-
ence spur varies with
, which is used here to verify
whether it is the dominant spur source. In [9], inverters as shown
in Fig. 5(a) are used to convert the sine wave crystal oscillator
(XO) into a steep square wave Ref. Now, the XO output is DC
biased to
with an off-chip bias-T and can be tuned
by tuning
. Fig. 5(b) shows the measured reference spur
variations of the design of [9] while tuning
. The shape
matches well with the simulated
. We can
conclude here that the BFSK effect is the major cause of the
poor reference spur in [9].
In order to suppress the BFSK effect, we propose to add a
dummy sampler as displayed in Fig. 4(b). The dummy sampler
is a copy of the existing sampler but is controlled by the inverted
Ref. Due to the complementary switching of the sampler and its
dummy, the VCO is always connected to one
. The VCO
capacitive load thus does not change over time and the BFSK
effect is compensated. In reality, this compensation is not perfect
due to mismatch in the sampling capacitor
. Since the
value of
is proportional to the square root of , (8)
becomes
(9)
where
is a process constant describing the matching prop-
erty of the sampling capacitor. The
factor rises because it is
the mismatch between two
. It is thus desirable to have a
small
for a low spur level. However, a smaller means
a larger
and more sampler noise [9]. There is thus a
tradeoff between the spur level and the in-band phase noise due
to the SSPD.
B. Charge Sharing/Injection
Apart from the BFSK effect, the VCO sampling activity also
brings two other mechanisms which disturb the VCO opera-
tion, namely charge injection from the sampling switches to the
VCO and charge sharing between the VCO and . While
the former can be canceled by adding dummy switches[6],
[7], the latter needs more effort to deal with. The VCO-
charge sharing occurs because the voltages on and the
VCO tank capacitor may not be equal when they are con-
nected at the switch-on moment, which can be explained using
Fig. 6. Without loss of generality, we assume that the sampling
switch is on when Ref is low and off when Ref is high (PMOS
switches are used in the design for practical reasons). The
Ref rising edge is then the sampling edge, i.e., the moment of
switch-off where holding starts and voltage is sampled. The Ref
falling edge is the tracking edge, i.e., the moment of switch-on
where tracking starts. After the PLL achieves locking, the
Ref sampling edge is aligned with a VCO zero-crossing. The
voltage on
at the switch-on moment is then well-defined
and equal to the VCO DC voltage:
,
where the symbol “!” is used to stress the specific moment
in time. In contrast, the voltage on the VCO tank capacitor
at the switch-on moment
depends on the position