474 • 2010 IEEE International Solid-State Circuits Conference
ISSCC 2010 / SESSION 26 / HIGH-PERFORMANCE & DIGITAL PLLs / 26.4
26.4 Spur-Reduction Techniques for PLLs Using Sub-
Sampling Phase Detection
Xiang Gao
1
, Eric A. M. Klumperink
1
, Gerard Socci
2
, Mounir Bohsali
2
,
Bram Nauta
1
1
University of Twente, Enschede, Netherlands
2
National Semiconductor, Santa Clara, CA
In PLL designs, a wide loop bandwidth is often desired as it offers fast settling
time, reduces on-chip loop filter area and sensitivity of the VCO to pulling. The
reference spur is a major issue when the bandwidth is increased, because rip-
ples on the VCO control line undergo less filtering by the loop filter. This paper
proposes design techniques based on sub-sampling phase detection to reduce
the reference spur of a 2.2GHz PLL to -80dBc at a high loop-bandwidth-to-ref-
erence-frequency ratio (
f
BW
/
f
ref
) of 1/20.
In a charge-pump (CP) PLL, the mismatch between the CP up current source I
UP
and down current source I
DN
is often the major source of reference spur. In a
conventional phase-frequency-detector (PFD)/CP as shown in Fig. 26.4.1(a), the
PFD converts the VCO phase error into the I
UP
and I
DN
switch-on time difference
(
t
UP,on
-
t
DN,on
). I
UP
and I
DN
thus have a
variable on-time
but
constant amplitude
fixed
by biasing. In case of I
UP
and I
DN
mismatch, one of them has to be on for a longer
time in order to reach the steady state condition that the net CP output charge is
zero. This causes CP output current ripple as shown in Fig. 26.4.1(a), and thus
reference spurs.
The sub-sampling PLL (SSPLL) in [1] achieves very low in-band phase noise at
low power. We will show now that it is intrinsically insensitive to CP mismatch
which can be exploited to also achieve a very low spur. The sub-sampling phase
detector (SSPD)/CP in the SSPLL is displayed in Fig. 26.4.1(b) [1]. The SSPD
samples the VCO with a reference clock
Ref
and converts the VCO phase error
into sampled voltage difference (
V
sam+
-
V
sam-
), which controls the amplitude of I
UP
and I
DN
. A block Pulser generates a pulse
Pul
, non-overlapping with
Ref
, and
switches on/off I
UP
and I
DN
simultaneously
. This Pulser controls the SSPD/CP
gain and functions as the second track-and-hold for the VCO sampling action.
Therefore, I
UP
and I
DN
have a
variable amplitude
but a
constant on-time
equal to
the width of
Pul
. Since I
UP
and I
DN
have equal on-time, the steady state condition
of zero net CP output charge is met only if I
UP
and I
DN
also have equal amplitude.
In other words, there will be no I
UP
and I
DN
mismatch. Actually, the PLL loop
tunes the amplitudes of I
UP
and I
DN
until they match, by shifting the locking point
away from the ideal point (VCO zero-crossing), see Fig. 26.4.1(b). The current
source switches still suffer from mismatch but their contribution to CP current
ripple is small.
Although the CP in Fig. 26.4.1(b) produces small ripple, the SSPD driving the CP
samples the VCO and thus can cause spurs. The sampler switching activity dis-
turbs the VCO operation in three ways: 1) charge sharing between the VCO and
sampling capacitors
C
sam
since the voltages on
C
sam
and VCO output may not be
equal when they are connected at the switch-on moment; 2) variation in the VCO
capacitive load and thus
f
VCO
when the switches connects/dis-connects the
SSPD/CP to the VCO; 3) charge injection from the sampling switches to the VCO.
Due to these effects, a poor reference spur of -46dBc was measured in [1]
although a buffer was used to isolate the VCO and SSPD.
Figure 26.4.2 shows the proposed architecture which overcomes the aforemen-
tioned spur issues. The core is a SSPLL similar to [1]. It uses a SSPD that uti-
lizes the
Ref
rising edge to sample the VCO. In steady state, the sampling edge,
i.e.
Ref
rising edge, is aligned with a VCO zero-crossing by the SSPLL loop. If
we can tune the
Ref
falling edge such that it is also aligned to a VCO zero-cross-
ing, the VCO voltages at the
Ref
rising/falling edges will be the same and there
is ideally no charge sharing between VCO and
C
sam
at the SSPD switch-on
moment. This is achieved by using a duty cycle controlled
Ref
buffer and a sub-
sampling DLL (SSDLL), see Fig. 26.4.2. In the
Ref
buffer, the crystal oscillator
(XO) directly controls the NMOS N1 while a pulse
V
GP
generated from the XO
with a delay Δt and a timing control circuit (TCC) controls the PMOS P1. The
timing is set such that the conduction time of P1 and N1 is non-overlapping. In
this way, the
Ref
rising edge is defined by XO via N1 (and the inverter thereafter)
while the
Ref
falling edge is independently defined by
V
GP
via P1. The
Ref
falling
edge can then be tuned by the DLL via tuning Δt, without affecting the
Ref
ris-
ing edge. The DLL uses the same SSPD/CP as the PLL, but its sampling clock
Ref
is the inverse of
Ref
. A transmission gate compensates the inverter delay.
The DLL thus uses the
Ref
rising edge to sample the VCO and aligns the
Ref
ris-
ing edge, i.e., the
Ref
falling edge to the VCO zero-crossing. Now, both the
Ref
rising and falling edges are aligned with the VCO zero-crossings and the condi-
tion for no charge sharing is achieved. Moreover, since there are now two iden-
tical SSPD/CP switched by complementary clocks, the VCO is either connected
to one or the other SSPD/CP and its capacitive load is kept constant. The com-
plementary way of switching also cancels the charge injection from the sampling
switches to the VCO. Therefore, all the three aforementioned SSPD related spur
mechanisms are largely suppressed. Since the DLL only controls the
Ref
falling
edge which is not the sampling edge for the PLL, it will not disturb the PLL oper-
ation nor add noise to the PLL output.
Figure 26.4.3 shows a detailed schematic of the SSPD/CP with Pulser. Since I
UP
and I
DN
mismatch will be tuned out by the PLL loop, the current sources’ output
impedance is not an issue and single transistors are used, which saves voltage
headroom. To achieve low CP ripple, the charge sharing between I
UP
and I
DN
drain nodes (d1 and d2 in Fig. 26.4.3) and the loop filter (LF) is another concern.
The CP thus uses a current steering topology, where I
UP
and I
DN
are either con-
nected to LF or dumped to a capacitor
C
dump
. Ideally, there is no charge sharing
if the voltages on d1 and d2 are kept constant during switching, i.e., if we can
set
V
LF
=
V
dump
. In a conventional CP, this requires a unity-gain buffer. Here, this is
achieved for free as explained below. In steady state, the net charge into the LF
and
C
dump
should be both zero. Since I
UP
and I
DN
have equal on-time in both ‘con-
nected to LF’ and ‘dumped to
C
dump
’ cases, they must also have equal amplitude
in both cases. This condition is met only if
V
LF
=
V
dump
, where the finite current
source output impedance is actually the equalizing mechanism.
The chip fabricated in a standard 0.18-µm CMOS process occupies an active
area of 0.2 mm
2
(Fig. 26.4.7). All circuitry uses 1.8V supply, while separate sup-
ply domains provide isolation. The 2.21GHz PLL tested with package consumes
3.8mW with <0.2mW in the DLL. The in-band phase noise is -121dBc/Hz at
200kHz as shown in Fig. 26.4.4. It is 5dB higher than that of [1], mainly because
here we used a several times smaller
C
sam
which helps reducing the spur level
but raises the noise contribution of the SSPD and its buffer. Fig. 26.4.5 shows
the reference spur measured from 20 samples. The worst case is –80dBc, 34dB
better than [1], and the best case is -85dBc. Fig. 26.4.6 displays a comparison
with other low spur PLLs in [2-5]. This design has the lowest spur, combined
with the lowest in-band phase noise as well as the lowest power consumption,
while using a high
f
BW
/
f
ref
of 1/20.
Acknowledgements:
The authors would like to thank A. Djabbari, K.Y. Wong, B. Zhang for useful dis-
cussions.
References:
[1] X. Gao,
et al.
, “A 2.2GHz 7.6mW Sub-Sampling PLL with -126dBc/Hz In-band
Phase Noise and 0.15ps
rms
Jitter in 0.18µm CMOS,”
IEEE Int. Solid-State Circuits
Conf. (ISSCC),
pp. 392 - 393, Feb. 2009.
[2] C. M. Hung and K. K. O, “A fully integrated 1.5-V 5.5-GHz CMOS phase-
locked loop,”
IEEE J. Solid-State Circuits
, vol. 37, pp. 521–525, Apr. 2002.
[3] S. Pellerano,
et al.
, “A 13.5-mW 5-GHz frequency synthesizer with dynamic-
logic frequency divider,”
IEEE Journal of Solid-State Circuits
, vol. 39, no. 2, pp.
378-383, Feb. 2004.
[4] C.-F. Liang, S.-H. Chen and S.-I. Liu, “A Digital Calibration Technique for
Charge Pumps in Phase-Locked Systems,”
IEEE J. Solid-State Circuits
, vol. 43,
no. 2, pp. 390 - 398, Feb. 2008.
[5] K. J. Wang, A. Swaminathan and I. Galton, “Spurious Tone Suppression
Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL,”
IEEE J.
Solid-State Circuits
, vol. 43, no. 12, pp. 2787 - 2797, Dec. 2008.
978-1-4244-6034-2/10/$26.00 ©2010 IEEE
475DIGEST OF TECHNICAL PAPERS •
ISSCC 2010 / February 10, 2010 / 3:15 PM
Figure 26.4.1: (a) Conventional 3-state PFD and timing controlled CP, (b) Sub-
sampling PD and amplitude controlled CP.
Figure 26.4.2: Block diagram of the PLL.
Figure 26.4.3: Schematic of SSPD/CP with Pulser.
Figure 26.4.5: (a) Measured reference spur level from 20 samples and (b) the
best case reference spur measured among the 20 samples using Agilent
E4440A Spectrum Analyzer.
Figure 26.4.6: PLL performance summary and comparison with low spur PLL
designs.
Figure 26.4.4: Measured PLL phase noise spectrum from an Agilent E5501B
phase noise measurement setup.
26
• 2010 IEEE International Solid-State Circuits Conference 978-1-4244-6034-2/10/$26.00 ©2010 IEEE
ISSCC 2010 PAPER CONTINUATIONS
Figure 26.4.7:
Chip micrograph.