SSTL based green image ALU design on different FPGA
01 Dec 2013-pp 146-150
TL;DR: In this article, a green image ALU is designed in Xilinx ISE 14.6 using different IO standard of SSTL in 40nm Virtex-6 and Spartan-6 FPGA.
Abstract: In this paper, green Image ALU is designed in Xilinx ISE 14.6 using different IO standard of SSTL in 40nm Virtex-6 and Spartan-6 FPGA. We are comparing different SSTL IO standard to get reduction in IO power. We accomplish energy efficiency with respect to low voltage impedance, by using SSTL technology. In this entire work, we are using different classes of SSTL and observe that when image ALU operates at 1THz device operating frequency with SSTL18_I_DCI I/O Standard using virtex-6 FPGA, there is 45.55% decrease in IO power and 20.50% in Clock power as compared to SSTL18_II IO Standard. Similarly when we operate Image ALU at 1THz using Spartan-6, there is 33.31% reduction in IO power of SSTL18_I with respect to SSTL18_II Standard. There are 16 different arithmetic and logic operations in Image ALU. The Clock power, Logic power and Signal power of Image ALU remains same using Spartan-6 I/O Standard.
Citations
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TL;DR: A power-efficient universal asynchronous receiver transmitter (UART) is implemented on 28 nm Artix-7 field-programmable gate array (FPGA) to reduce the power utilization of UART with the FPGA device in industries.
Abstract: In the present scheme of the world, the problem of shortage of power is seen across the world which can be a vulnerability to various communication securities. The scope of proposed research is that it is a step towards completing green communication technology concepts. In order to improve energy efficiency in communication networks, we designed UART using different nanometers of FPGA, which consumes the least amount of energy. This shortage is happening because of expanding of industries across the world and the rapid growth of the population. Therefore, to save the power for our upcoming generation, the globe is moving towards the concept and ideas of green communication and power-/energy-efficient gadget. In this work, a power-efficient universal asynchronous receiver transmitter (UART) is implemented on 28 nm Artix-7 field-programmable gate array (FPGA). The objective of this work is to reduce the power utilization of UART with the FPGA device in industries. To do this, the same authors have used voltage scaling techniques and compared the results with the existing FPGA works.
77 citations
22 Apr 2014
TL;DR: This work has used Verilog as HDL and Xilinx ISE 14.6 as simulator to design the voltage based efficient fire sensor and has used four different kinds of Stub Series Terminated Logic (SSTL)IO standards.
Abstract: In this paper an approach is made to design the voltage based efficient fire sensor and for that reason we have used four different kinds of Stub Series Terminated Logic (SSTL)IO standards. Airflow and heat sink are main parameters while analyzing the thermal dissipation in the circuit. In this work we have taken two values for LFM i.e. 250, 500 and three profiles for heat sink are taken, these are low profile, medium profile and high profile. When the voltage sensor is operating at 1THz and LFM is 250 with low profile heat sink, junction temperature of SSTL135_DCI is reduced up to 5.12% 6.03% and 20.77% as compared to SSTL12, SSTL12_DCI and SSTL135_R respectively. Under same operating frequency and heat sink profile with LFM as 500, we are achieving 3.69%, 5.22% and 17.99% less junction power reduction in SSTL135_DCI with respect to SSTL12, SSTL12_DCI and S S TL135_Rrespectively. This design is implemented on Kintex-7 FPGA, XC7K70T device and −3 speed grades. In this work we have used Verilog as HDL and Xilinx ISE 14.6 as simulator.
17 citations
Cites methods from "SSTL based green image ALU design o..."
...In [5], with the help of different types of SSTL IO standards, it is analyzed that on operating image ALU with 1THz frequency on virtex-6 FPGA clock power and IO power of SSTL18_I_DCI is reduced up to 45....
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TL;DR: There is 50-60% reduction in power dissipation, which is possible with proper selection of the most energy efficient IO standards i.e. SSTL135_R among S STL logic families.
Abstract: In this particular work, we have done power dissipation analysis of DES algorithm, implemented on 28nm FPGA. We have used Xilinx ISE software development kit for all the observation done in this particular research work. Here, we have taken SSTL (StubSeries Terminated Logic) as input-output standard. We have considered six subcategories of SSTL (i.e. SSTL135, SSTL135_R, SSTL15, SSTL15_R, SSTL18_I and SSTL18_II) for four different WLAN frequencies (i.e. 2.4GHz, 3.6GHz, 4.9GHz, and 5.9GHz). We have done analysis considering five basic powers i.e. clock power, logic power, signal power, IOs power, leakage power and total power. There is 50-60% reduction in power dissipation, which is possible with proper selection of the most energy efficient IO standards i.e. SSTL135_R among SSTL logic families.
16 citations
Cites methods from "SSTL based green image ALU design o..."
...%) is used by algorithm with 28nm FPGA....
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...One scientist have used different IO standard of SSTL in 40 nm Virtex-6 and Spartan-6 FPGA [3], Where as we have used SSTL IO standard in 28nm Artix-7 FPGA for comparing different SSTL IO standard to get reduction in IO power....
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...We can also use 16nm ultra scale FPGA and 3-...
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...ISSN: 1738-9976 IJSIA Copyright ⓒ 2015 SERSC In this particular work, we have done power dissipation analysis of DES algorithm, implemented on 28nm FPGA....
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...In this particular research work, we have done power analysis of DES algorithm, which is implemented on 28nm FPGA using SSTL as input-output standard....
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01 Nov 2014
TL;DR: This work is operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use, using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator.
Abstract: Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the impedance of line, port and device of our design under consideration. Therefore, selection of energy efficient SSTL I/O standard among available different class of SSTL logic family in FPGA, plays a vital role to achieve energy efficiency in design under test (DUT). Here, DUT is ROM. ROM is an integral part of processor. Therefore, energy efficient design of RAM is a building block of energy efficient processor. We are using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator. We are operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use. When there is no demand of peak performance, then we can save 74.5% clock power, 75% signal power, and 30.83% I/O power by operating our device with 1GHz frequency in place of 4GHz. There is no change in clock power and signal power but SSTL2_H_DCI having 80.24% 83.38% 62.92% and 76.52% and 83.03% more I/O power consumption with respect to SSTL2_I, SST18_I, SSTL2_I_DCI, SSTL2_II, and SSTL15 respectively at 3.3GHz.
14 citations
Cites background from "SSTL based green image ALU design o..."
...1818978-9-3805-4416-8/15/$31.00 c©2015 IEEE The primary purpose of using HSTL I/O standard is to avoid transmission line reflection by matching the impedance of transmission line, device, input port and output port....
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22 Apr 2014
TL;DR: This paper proposes HSTL based energy efficient design of frame buffer for a digital image processor and implemented on both Virtex-6 FPGA and Airtex-7 FPGa and compared the power dissipation.
Abstract: This paper proposes HSTL based energy efficient design of frame buffer for a digital image processor. Our aim is to make energy efficient frame buffer design and for that reason we are using different types of HSTL IO standards. This design is implemented on both Virtex-6 FPGA and Airtex-7 FPGA and compared the power dissipation. It is observed that at 1GHz operating frequency, there is maximum IO power reduction of 79.49% for HSTL_I IO standard with Airtex-7 FPGA as compared to Virtex-6 FPGA. For HSTL_II_18, at 1THz, we are getting minimum IO power reduction of 5.90% with Virtex-6 FPGA as compared to Airtex-7 FPGA. For Airtex-7 FPGA, XC7A100T device, −3 speed grades, and CSG2324 package is used and For Virtex-6 FPGA, XC6VLX75T, −1 speed grade and FF484 package is used.
12 citations
Cites methods from "SSTL based green image ALU design o..."
...The work in [5], shows the use of SSTL IO standard and Image ALU is taken as target circuit and by observation it is observed that with Virtex-6 FPGA and at 1GHz frequency, there is 45....
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References
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10 Apr 2013
TL;DR: There is 67.04% dynamic power reduction with LVCMOS12 when the authors migrate from 90-nm Spartan-3 FPGA to 40-nm Virtex-6FPGA, and there is 81.19%, 92.05% and 73.41% dynamicPower reduction in ALU with LVDCI IO standard in place of LVD CI_DV2, HSTL_I, and LVCmOS12 respectively.
Abstract: There is 67.04% dynamic power reduction with LVCMOS12 when we migrate from 90-nm Spartan-3 FPGA to 40-nm Virtex-6 FPGA. There is 81.19%, 92.05% dynamic power reduction when using LVCMOS12 in place of HSTL_II_18 and SSTL2_I_DCI respectively. We achieved 65.56%, 72.59% and 73.41% dynamic power reduction in ALU with LVDCI IO standard in place of LVDCI_DV2, HSTL_I, and LVCMOS12 respectively. There is 68.34% and 52.51% dynamic power reduction in ALU when using LVCMOS12 and LVCMOS15 in place of LVCMOS25. There is 62.45% dynamic power reduction in ALU, when we use HSTL_I in place of SSTL2_I_DCI. Power is directly proportional to frequency. With increase in frequency, there is increase in power consumption irrespective of IO standard. LVCMOS is the only IO standard, which takes less power when we upgrade our design to latest FPGA.
37 citations
"SSTL based green image ALU design o..." refers methods in this paper
...In our task, we are extending our work from LVCMOS in [4] to different IO standard of SSTL on different series of FPGA (Virtex-6 and Spartan-6)....
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11 Apr 2013
TL;DR: The effect of using digitally controlled impedance IO Standard in memory interface design in terms of power consumption is studied and 50% dynamic power reduction is achieved.
Abstract: In this paper, we study the effect of using digitally controlled impedance IO Standard in memory interface design in terms of power consumption. In this work, we achieved 50% dynamic power reduction at 1.5V output driver voltage, 35.2% dynamic power reduction at 1.8V output driver voltage in comparison to 2.5V output driver voltage in DCI based IO standard implementation on input or output port in target design. Target device XC6VLX75TFF484-1 is a Virtex-6 FPGA of -1 speed grade and 484 pins is used for implementation of this design. Target Design is RAM-UART memory interface. XPower 13.4 is used for power analysis of our low power memory interface design. ISim is simulator to generate waveform. Planahead is used for design, synthesis and implementation.
22 citations
"SSTL based green image ALU design o..." refers background or methods in this paper
...In [2], 50% dynamic power reduction achieved at 1....
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...In [2], influence of digitally controlled impedance IO Standard in reduced power memory design is under consideration....
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...We are extending our task from DCI to different IO standard of SSTL on FPGA and also shift from memory (in [2]) to Image ALU....
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22 Nov 2004
TL;DR: An image recognition processor, utilizing a phase only correlation (POC) algorithm, that can perform 2D 512/spl times/512 pixel image recognition within 105.2 ms and using 310.9 mW of power is proposed.
Abstract: An image recognition processor, utilizing a phase only correlation (POC) algorithm is proposed. The arithmetic logical unit (ALU) in this processor can be re-configured dynamically. By arranging the POC algorithm to a form suitable for reconfigurable computing, the proposed processor can perform 2D 512/spl times/512 pixel image recognition within 105.2 ms and using 310.9 mW of power. This power consumption is 11.3 times lower than that of a previously reported work with same execution time.
8 citations
"SSTL based green image ALU design o..." refers background or methods in this paper
...The arithmetic logical unit (ALU) in [5] can be re-configured dynamically....
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...In [5], an image recognition processor, utilizing a phase only correlation (POC) algorithm is proposed....
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04 Mar 2013
TL;DR: Experimental results on ISCAS85 and 74X-Series benchmark circuits show that the power consumption of 8-bit ALU based on this approach can be reduced by 54%-60% for different frequency levels as compared to the conventional dynamic ALU design.
Abstract: In this paper, we propose an application-driven ALU design methodology to achieve high level of power efficiency for modern microprocessors. We introduce a PN selection algorithm (PNSA) which enables designers to select power efficient dynamic modules for different applications, based on the detailed analysis of dynamic circuits. Experimental results on ISCAS85 and 74X-Series benchmark circuits show that the power consumption of 8-bit ALU based on this approach can be reduced by 54%-60% for different frequency levels as compared to the conventional dynamic ALU design, demonstrating the effectiveness of the proposed method on application-driven custom ALU design.
5 citations
"SSTL based green image ALU design o..." refers methods in this paper
...For modern processor to achieve high level of power efficiency, an application precise ALU design methodology is proposed in [3]....
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23 May 1989
TL;DR: The authors show that a VLSI implementation using either a SIMD or an RPA (reconfigurable processor array) can be used to process a 128*128 image at a 10 ms cycle rate with an effective throughput of 100 MOPS.
Abstract: Real time signal processing implemented with VLSI chips is used to find an aimpoint on one object in a set of objects that were imaged in the focal plane. The authors explain the function of each of the algorithm steps needed and show that a VLSI implementation using either a SIMD (single-instruction-multiple-data) or an RPA (reconfigurable processor array) can be used to process a 128*128 image at a 10 ms cycle rate with an effective throughput of 100 MOPS. The alternative RPA solution, which is based on existing VLSI LINC (link and interconnect chip) and ALU SlP (scan line processor) chips, is presented. The RPA approach can only achieve the cycle time constraint when the clustering is performed by a specialized VLSI chip. Although the image processing function is more compatible with the SIMD approach, the RPA approach using the clustering chip is shown to require far fewer VLSI chips. >
2 citations
"SSTL based green image ALU design o..." refers methods in this paper
...In [6], Real time signal processing design with VLSI is used to discover an aim point on one object in the set of objects that were imaged in the focal plane....
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