SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA

HSTL IO Standards Based Processor Specific Green Counter Design on 90nm FPGAAbhay Saxena

Abstract: Extending battery life and increase in portability of modern electronic devices and gadgets are the main motives behind the Green Computing which is also known by similar terms like energy efficient design or low power design or green design. Such efficiency is only possible if all the components of processor are also energy efficient. In this work, the researchers tried to analyze the energy optimization possibility in counter design by selection of energy efficient IO standards. The researchers had used High Speed Transceiver Logic for the purpose of energy efficient counter design on Spartan3 (90nm) FPGA (field-programmable gate array) using VHDL (VHSIC Hardware Description Language) hardware description language along with the Xilinx ISE simulator for the analysis and synthesis of counters. Spartan 3 with 90 nm low power is used to achieve substantial power savings. Here, researchers have used five different HSTL IO standards for this work. The standards used are HSTL_I, HSTL_III, HSTL_III_18, HSTL_III_DCI and HSTL_II_18. With these sets of IO standards, Researchers had run their counter design on various device operating frequencies (1.0 GHz to 4.0 GHz). The results clearly indicate that this dynamic frequency (1.0 GHz in lieu of 4.0 GHz) scaling had saved 45% of total power.

GTL based Internet of Things enable processor specific RAM design on 65nm FPGA

Abstract: In this work, we Energy Efficient Internet of Things (IoTs) Enable RAM is presented. In order to make it energy efficient, used Gunning Transceiver Logic (GTL) IO Standard and Gunning Transceiver Logic Plus (GTLP). We used the 4 different members of GTL and GTLP IO standards family and searched the most energy efficient among them. We observed that when we use 3.6 GHz operating frequency, there is 90.2% reduction in I/O power when we used GTL instead of GTLP_DCI. We have inserted a 128-bit IP address in RAM to make internet of things enable RAM. Finally, we operated our IOTs Enable RAM with different operating frequency of I3, I5, I7, Moto-E and Moto-X.

SSTL Based Energy Efficient FIFO Design for High Performance Processor of Portable Devices

Abstract: for High Performance Processor of Portable Devices Abhay Saxena , Sanjeev Kumar Sharma , Pragya Agarwal Chandrashekhar Patel #4 #1,3,4 Department of Computer Science DSVV Haridwar, India 1 abhaysaxena2009@gmail.com 3 pragyaagarwal30@gmail.com shekharrockin1988@gmail.com *2 JP Institute of Engineering and Technology Meerut, India 2 dean.ar@jpiet.com Abstract— Now days green computing is major research area in the computer science field, where we want to reduce the total power consumption of our device by applying different techniques .Having this concern we have designed our FIFO (First In First Out) circuit and calculated its total power dissipation at different-different families of SSTL with frequency scaling techniques. In this technique we used following (20 GHz, 40GHz, 60 GHz and 80 GHz ) frequency range. In our work first we have worked with SSTL12 and found that when we scaled down the frequency from 80 GHz to 20 GHz 71.55% reduction in total IO power. In second we have worked with SSTL15 and got 74.02% of reduction in total IO power when we reduced frequency from 80 GHz to 20 GHz. In last we worked with SSTL18_I and SSTL18_II and found 74.29% and 74.28% of reduction in total power respectively, when we scaled down the frequency from 80 GHz to 20 GHz. We have designed our FIFO on 28 nm kintex-7 FPGA family

SSTL IO standard based power efficient data processing device design on FPGA

Abstract: In this paper, we have designed a power efficient data center using SSTL I/O standards. We have compared the performance of our data processing device through different processors. To increase the performance, Stub-Series Terminated Logic I/O standards are used. 17 distinct functions were performed on DPD that calculated the capability of four distinct processors. At operating frequency of 1.9 GHz of AMD x2150, a significant reduction of clock power, logic power and signal power is observed as 84.47%, 45% and 41.02% respectively. Minimization in DSP power, IO power is 44.4% & 18% respectively when we apply AMD x2150 at 1.9GHz in preference to Intel Xeon E7-8893, operating at 3.4 GHz. By doing the analysis, the best results are obtained while using AMD x2150 at 1.9GHz. This paper provides a novel FPGA based design for power efficient data processing device.

Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA

Abstract: In this work, we are making energy efficient ALU using the most energy efficient LVCMOS IO standard for the highest frequency of i7 processor. It is observed that LVCMOS12 is the most energy efficient than all available LVCMOS having 26.23, 58.37 and 75.65 % less IO power reduction than LVCMOS18, LVCMOS25 and LVCMOS33 respectively at 1 GHz. Then we are making this ALU portable using MOBILE DDR IO standard in place of default LVCMOS33 IO standard which we use in traditional ALU. As we replace LVCMOS with MOBILE DDR, we are achieving 69.07 % portability in terms of IO power and 29.36 % in terms of Leakage power at 2.9 GHz. In next stage, we try to enhance the performance of ALU with MOBILE DDR but not beyond the power consumption with LVCMOS. In that way, we achieve the highest frequency of 12 GHz with MOBILE DDR. That was earlier possible for 3.8 GHz 64-bit ALU using CMOS. In this HDL based implementation of 64-bit ALU on FPGA, Kintex-7 FPGA is used with XC7K70T device and FBG676 package is used.

Leakage current reduction in vlsi systems

Abstract: There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits remain in stand-by (or sleep) mode significantly longer than in active mode, their stand-by current, and not their active switching current, determines their battery life. Hence, stringent specifications are being placed on the stand-by (or leakage) current drawn by such devices. As the power supply voltage is reduced, the threshold voltage of transistors is scaled down to maintain a constant switching speed. Since reducing the threshold voltage increases the leakage of a device exponentially, leakage current has become a dominant factor in the design of VLSI circuits. In this paper, we describe a method that uses simultaneous dynamic voltage scaling (DVS) and adaptive body biasing (ABB) to reduce the total power consumption of a processor under dynamic computational workloads. Analytical models of the leakage current, dynamic power, and frequency as a function of supply voltage and body bias are derived and verified with SPICE simulation. Given these models, we show how to derive an analytical expression for the optimal trade-off between supply voltage and body bias, given a required clock frequency and duration of operation. The proposed method is then applied to a processor and is compared with DVS alone for workloads obtained using real-time monitoring of processor utilization for four typical applications.

SSTL based green image ALU design on different FPGA

Abstract: In this paper, green Image ALU is designed in Xilinx ISE 14.6 using different IO standard of SSTL in 40nm Virtex-6 and Spartan-6 FPGA. We are comparing different SSTL IO standard to get reduction in IO power. We accomplish energy efficiency with respect to low voltage impedance, by using SSTL technology. In this entire work, we are using different classes of SSTL and observe that when image ALU operates at 1THz device operating frequency with SSTL18_I_DCI I/O Standard using virtex-6 FPGA, there is 45.55% decrease in IO power and 20.50% in Clock power as compared to SSTL18_II IO Standard. Similarly when we operate Image ALU at 1THz using Spartan-6, there is 33.31% reduction in IO power of SSTL18_I with respect to SSTL18_II Standard. There are 16 different arithmetic and logic operations in Image ALU. The Clock power, Logic power and Signal power of Image ALU remains same using Spartan-6 I/O Standard.

Simulation of voltage based efficient fire sensor on FPGA using SSTL IO standards

Abstract: In this paper an approach is made to design the voltage based efficient fire sensor and for that reason we have used four different kinds of Stub Series Terminated Logic (SSTL)IO standards. Airflow and heat sink are main parameters while analyzing the thermal dissipation in the circuit. In this work we have taken two values for LFM i.e. 250, 500 and three profiles for heat sink are taken, these are low profile, medium profile and high profile. When the voltage sensor is operating at 1THz and LFM is 250 with low profile heat sink, junction temperature of SSTL135_DCI is reduced up to 5.12% 6.03% and 20.77% as compared to SSTL12, SSTL12_DCI and SSTL135_R respectively. Under same operating frequency and heat sink profile with LFM as 500, we are achieving 3.69%, 5.22% and 17.99% less junction power reduction in SSTL135_DCI with respect to SSTL12, SSTL12_DCI and S S TL135_Rrespectively. This design is implemented on Kintex-7 FPGA, XC7K70T device and −3 speed grades. In this work we have used Verilog as HDL and Xilinx ISE 14.6 as simulator.

IO standard based energy efficient ALU design and implementation on 28nm FPGA

Abstract: In this work, target design is ALU. To achieve reduction in IOs power we are searching the most energy efficient LVCMOS(Low Voltage Complementary Metal Oxide Semiconductor) IO standard, whose power consumption is less in compare to other IO standard. There is 85.18% power reduction when we migrate from LVCMOS33 based ALU design to LVCMOS12 based ALU design. There is 41.45% power reduction when we migrate from LVCMOS33 based ALU design to LVCMOS25 based ALU design. Target FPGA family is 28nm Artix-7. Verilog is hardware description language used for design of ALU. There is 7.16% reduction in power for only LVCMOS15, when we change drive strength from 16 milliAmpere to 8 milli-Ampere. There is 5.44% reduction in power for LVCMOS18 when we change drive strength from 24 milliAmpere to 8 milli-Ampere. LVCMOS33 is the highest power consumer and LVCMOS12 is the lowest power consumer among the different available LVCMOS IO standard when there is common drive strength applied.