Standard Cell Characterization for Reversible Logic
01 Sep 2016-pp 534-538
TL;DR: The design and standard cell characterization of the reversible logic is depicted and the Cadence® Liberate tool has been used in the designs and 45nm CMOS technology library files have been employed.
Abstract: In the recent years, the circuit complexity has been on massive rise. Manual designing of the complex chips are no longer possible. This situation has led to the proliferation of automated Electronic Design Automation (EDA) tools. These have also have lead to the development of the standard cell design methodologies and the semi custom design solutions. The standard cell can be used for a particular function and this eases the design segment manpower and effort. Secondly, the complex circuits in dire necessity of low power operation, necessitates the non-conventional low power design methodologies such as the reversible logic. They play a significant role in the design of digital circuits due to its distinguishing feature of incurring low power dissipation. This paper portrays the design and standard cell characterization of the reversible logic. The Cadence® Liberate tool has been used in the designs and 45nm CMOS technology library files have been employed.
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01 Jan 2021
TL;DR: In this article, different designs of 8 * 8 bit Vedic multiplier are implemented with different adders, and these multipliers and adders are structured using suitable reversible logic gates, that is, Feynman gate, Peres gate, Toffoli gate, DPG gate and modified Fredkin gate.
Abstract: Multiplier is one among the essential hardware blocks in present-day communication and digital signal processing (DSP) systems. The primary advantage of Vedic multiplier is that delay increases slowly with the increase of input bits. Vedic multiplier has supreme advantage when compared with other multipliers over regularity of structures and gate delays. In this paper, the different designs of 8 * 8 bit Vedic multiplier are implemented with different adders, and these multipliers and adders are structured using suitable reversible logic gates, that is, Feynman gate, Peres gate, Toffoli gate, DPG gate and modified Fredkin gate. The different designs of Vedic multipliers designed with the help of different adders, that is, ripple carry adder, carry skip adder and carry select adder, and hence compared their implementation time as well as area required for the circuitry. This comparison will help designers to choose the preferable multiplier according to the application specific demands.
2 citations
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IBM1
TL;DR: This result makes plausible the existence of thermodynamically reversible computers which could perform useful computations at useful speed while dissipating considerably less than kT of energy per logical step.
Abstract: The usual general-purpose computing automaton (e.g.. a Turing machine) is logically irreversible- its transition function lacks a single-valued inverse. Here it is shown that such machines may he made logically reversible at every step, while retainillg their simplicity and their ability to do general computations. This result is of great physical interest because it makes plausible the existence of thermodynamically reversible computers which could perform useful computations at useful speed while dissipating considerably less than kT of energy per logical step. In the first stage of its computation the logically reversible automaton parallels the corresponding irreversible automaton, except that it saves all intermediate results, there by avoiding the irreversible operation of erasure. The second stage consists of printing out the desired output. The third stage then reversibly disposes of all the undesired intermediate results by retracing the steps of the first stage in backward order (a process which is only possible because the first stage has been carried out reversibly), there by restoring the machine (except for the now-written output tape) to its original condition. The final machine configuration thus contains the desired output and a reconstructed copy of the input, but no other undesired data. The foregoing results are demonstrated explicitly using a type of three-tape Turing machine. The biosynthesis of messenger RNA is discussed as a physical example of reversible computation.
3,497 citations
Posted Content•
TL;DR: In this paper, a linear-depth ripple-carry quantum addition circuit with only a single ancillary qubit has been proposed, which has lower depth and fewer gates than previous ripple carry adders.
Abstract: We present a new linear-depth ripple-carry quantum addition circuit. Previous addition circuits required linearly many ancillary qubits; our new adder uses only a single ancillary qubit. Also, our circuit has lower depth and fewer gates than previous ripple-carry adders.
396 citations
"Standard Cell Characterization for ..." refers methods in this paper
...Quantum cost, delay, ancilla input and garbage outputs are some of the metrics used for validating ant reversible logic circuit [2]....
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02 Mar 2015
TL;DR: The use of Negative control lines for detecting overflow logic of BCD adder is explored which considerably reduces Quantum cost, delay and gate count which result in high speed B CD adder with optimized area which give way to lot of scope in the field of reversible computing in near future.
Abstract: Reversible logic has emerged as a possible low cost alternative to conventional logic in terms of speed, power consumption and computing capability. An adder block is a very basic and essential component for any processor and optimized design of these adders' results in efficient processors. In this work we propose optimized Binary adders and BCD adders. The adders designed in this work are optimized for Quantum cost, Delay and Area. A modified BCD adder is also proposed which removes redundancy in the circuit and acts as most efficient BCD adder. Here we explore the use of Negative control lines for detecting overflow logic of BCD adder which considerably reduces Quantum cost, delay and gate count which result in high speed BCD adder with optimized area which give way to lot of scope in the field of reversible computing in near future.
11 citations
"Standard Cell Characterization for ..." refers background in this paper
...An improved reversible circuit can be said to be designed, if the gate follows all these constraints [6]....
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01 Jan 2012
TL;DR: The standard cell gate library described here is a first investigation towards a computer aided design flow for reversible logic that includes cell placement and routing and the connection between the standard cells and a combinator-based reversible functional languages is described.
Abstract: This technical report shows the design and layout of a library of three reversible logic gates designed with the standard cell methodology. The reversible gates are based on complementary pass-transistor logic and have been validated with simulations, a layout vs. schematic check, and a design rule check. The standard cells have been used in the design and layout of a novel 4-bit reversible arithmetic logic unit. After validation this ALU has been fabricated and packaged in a DIL48 chip. The standard cell gate library described here is a first investigation towards a computer aided design flow for reversible logic that includes cell placement and routing. The connection between the standard cells and a combinator-based reversible functional languages is described.
10 citations
"Standard Cell Characterization for ..." refers background in this paper
...Using the standard cell of reversible logic, complex circuits can be designed very easily [10] [11] [12]....
[...]
TL;DR: An analytical timing model relating all TCPs with Cl and TR values for inverter standard cell and the relationship between the cell size and the model coefficients is derived and used in reducing number of HSPICE simulations in ECSM re-characterization significantly.
Abstract: Increasing the accuracy of circuit delay estimation using Non Linear Delay Model (NLDM) in nanometer range CMOS technologies is highly challenging. To solve this issue, people have started using effective current source model (ECSM) and composite current source model (CCSM), which can both be derived from each other. For a standard cell, ECSM stores certain predefined threshold crossing points (TCPs) of the output voltage waveform with respect to several input transition time (T
R
) and load capacitance (C
l
) values. In this work, we propose an analytical timing model relating all TCPs with Cl and TR values for inverter standard cell. We derive the relationship between the cell size and the model coefficients. We also derive the region of validity of the model in (T
R
, C
l
) space and determine its relationship with cell size. The proposed model is in good agreement with HSPICE simulations with a maximum error of 2.5%. We use this model and the derived relationships with cell size to reduce the number of simulations in ECSM library characterization. Due to process, voltage and on-chip temperature (PVT) variation, re-characterization is done at several PVT corners. In addition, layout dependent effects also lead to an unexpected variation in cell performance. To reduce the characterization effort, we derive relationships of variation of our model coefficients and regions of validity with cell size in mechanical stress enabled CMOS technologies, considering cell layout parameters. We also derive relationships of our model's coefficients with on-chip supply voltage and temperature variations. We use these relationships in reducing number of HSPICE simulations in ECSM re-characterization significantly.
7 citations
"Standard Cell Characterization for ..." refers background in this paper
...Using the standard cell of reversible logic, complex circuits can be designed very easily [10] [11] [12]....
[...]