Statistical analysis of BTI in the presence of process-induced voltage and temperature variations
29 Apr 2013-pp 594-600
TL;DR: An analytical model is developed to predict the probability density function and covariance of temperatures and voltage droops of a die in the presence of the BTI and process variation and it is observed that for benchmark circuits, treating each aspect independently and ignoring their intrinsic interactions results in 16% over-design, translating to unnecessary yield and performance loss.
Abstract: In nano-scale regime, there are various sources of uncertainty and unpredictability of VLSI designs such as transistor aging mainly due to Bias Temperature Instability (BTI) as well as Process-Voltage-Temperature (PVT) variations. BTI exponentially varies by temperature and the actual supply voltage seen by the transistors within the chip which are functions of leakage power. Leakage power is strongly impacted by PVT and BTI which in turn results in thermal-voltage variations. Hence, neglecting one or some of these aspects can lead to a considerable inaccuracy in the estimated BTI-induced delay degradation. However, a holistic approach to tackle all these issues and their interdependence is missing. In this paper, we develop an analytical model to predict the probability density function and covariance of temperatures and voltage droops of a die in the presence of the BTI and process variation. Based on this model, we propose a statistical method that characterizes the life-time of the circuit affected by BTI in the presence of process-induced temperature-voltage variations. We observe that for benchmark circuits, treating each aspect independently and ignoring their intrinsic interactions results in 16% over-design, translating to unnecessary yield and performance loss.
Citations
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01 Jun 2014
TL;DR: In this article, a framework is proposed to analyze the impact of NBTI, PBTI and hot carrier injection (HCI) on state-of-the-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism.
Abstract: Negative bias temperature instability (NBTI), positive bias temperature instability (PBTI) and hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this paper, a framework is proposed to analyze the impact of NBTI, PBTI and HCI on state-of-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism. Our methodology finds the detailed electrical stress and temperature of each device within a microprocessor system running a variety of standard benchmarks. Combining the electrical stress profiles, thermal profiles, and device-level models, we do timing analysis on the critical paths of a microprocessor using our methodology to characterize microprocessor performance degradation due to BTI and HCI. In addition, we study DC noise margins in conventional 6T SRAM cells as a function of BTI and HCI degradation to provide insights on reliability of memories embedded within microprocessors under realistic use conditions.
34 citations
TL;DR: This work presents an aging- and variationaware representative path selection technique based on machine learning that allows to measure the delay of a small set of paths and infer thedelay of a larger pool of paths that are likely to fail due to delay variations.
Abstract: Process together with runtime variations in temperature and voltage, as well as transistor aging, degrade path delay and may eventually induce circuit failure due to timing variations. Therefore, in-field tracking of path delays is essential, and to respond to this need, several delay sensor designs have been proposed in the literature. However, due to the significant overhead of these sensors and the large number of critical paths in today's IC, it is infeasible to monitor the delay of every critical path in silicon. We present an aging- and variationaware representative path selection technique based on machine learning that allows to measure the delay of a small set of paths and infer the delay of a larger pool of paths that are likely to fail due to delay variations. Simulation results for benchmark circuits highlight the accuracy of the proposed approach for predicting critical-path delay based on the selected representative paths.
30 citations
Cites background or methods from "Statistical analysis of BTI in the ..."
...Note that the localization information can be used by .negrained aging mitigation techniques such as input vector control (IVC) [Firouzi et al. 2013b], to focus on targeted gates/paths rather than treating the circuit (all critical paths) uniformly....
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...Runtime variations, including voltage and temperature .uctuations, are caused by the instantaneous switching current drawn from the power-grid network and .uctuations in chip activity, respectively [Firouzi et al. 2013]....
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TL;DR: A framework to perform timing analysis of state-of-art microprocessors considering the impact of process-voltage-temperature (PVT) variations and the aging effect, including bias temperature instability, hot carrier injection, and time-dependent dielectric breakdown is proposed.
Abstract: A framework is proposed to perform timing analysis of state-of-art microprocessors considering the impact of process-voltage-temperature (PVT) variations and the aging effect, including bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB). In this work, not only statistical timing analysis (StTA) due to each wearout mechanism is studied individually, but also the performance degradation while all these wearout mechanisms happen simultaneously is analyzed. Moreover, this work takes into account realistic use scenarios which include active, standby, and sleep modes. A unified gate-delay model, which combines both PVT variations and the aging effect, is constructed via a technique called multivariate adaptive regression splines (MARSP). Then a timing engine, which consists of two parts: a block-based analyzer and a path-based analyzer, is built to perform PVT-reliability-aware timing analysis. The accuracy and effectiveness of our framework has been verified on large industrial designs, like the LEON3 microprocessor, through a comparison with SPICE.
21 citations
Additional excerpts
...[3] and [4] propose a framework to study the BTI effect using an iterative scheme to deal with the interdependence between temperature and power profiles, together with BTI degradation....
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TL;DR: A framework is proposed to analyze the impact of BTI (NBTI and PBTI) and HCI on state-of-art microprocessors and to estimate microprocessor lifetimes due to each wearout mechanism.
Abstract: Negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this paper, a framework is proposed to analyze the impact of BTI (NBTI and PBTI) and HCI on state-of-art microprocessors and to estimate microprocessor lifetimes due to each wearout mechanism. Our methodology finds the detailed electrical stress and the temperature of each device within a microprocessor system running a variety of standard benchmarks. Combining the electrical stress profiles, thermal profiles, and device-level models, we perform timing analysis on the critical paths of a microprocessor using our methodology to characterize the microprocessor performance degradation due to BTI and HCI and to estimate the lifetime distribution of logic blocks. In addition, we study dc noise margins in conventional 6T SRAM cells as a function of BTI and HCI degradation to estimate memory lifetime distributions. The lifetimes of memory blocks are then combined with the lifetimes of logic blocks to provide an estimate of the system lifetime distribution.
19 citations
Cites background from "Statistical analysis of BTI in the ..."
...This can be included through iterations, as in [10]....
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13 Jun 2013
TL;DR: A framework to study wearout of state-of-the-art microprocessor systems is developed and a methodology to accurately estimate the lifetime due to each mechanism is presented.
Abstract: In this paper, we have developed a framework to study wearout of state-of-the-art microprocessor systems. Taking into account the detailed thermal and electrical stress profiles, which are determined by running benchmarks on the system, we present a methodology to accurately estimate the lifetime due to each mechanism. The lifetime-limiting blocks and paths of a circuit are highlighted using standard benchmarks.
14 citations
References
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TL;DR: In this article, the authors present formulas and tables that permit approximations to the moments in case n > 2, where the moments are approximated by iteration of a three-parameter computation or, alternatively, through successive use of the threeparameter table, which is given.
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675 citations
"Statistical analysis of BTI in the ..." refers background in this paper
...In the first phase, nominal power of each grid is calculated by adding up the power of the gates located in the grid (without considering the effect of process variations)....
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09 Nov 2003
TL;DR: An efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay while incorporating the effects of spatial correlations of intra-die parametervariations, using a method based on principal component analysis.
Abstract: We present an efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay while incorporating the effects of spatial correlations of intra-die parameter variations, using a method based on principal component analysis. The method uses a PERT-like circuit graph traversal, and has a run-time that is linear in the number of gates and interconnects, as well as the number of grid partitions used to model spatial correlations. On average, the mean and standard deviation values computed by our method have errors of 0.2% and 0.9%, respectively, in comparison with a Monte Carlo simulation.
561 citations
01 Sep 2006
TL;DR: This paper presents a predictive model for the negative bias temperature instability (NBTI) of PMOS under both short term and long term operation based on the reaction-diffusion (R-D) mechanism, which accurately captures the dependence of NBTI on the oxide thickness, the diffusing species and other key transistor and design parameters.
Abstract: This paper presents a predictive model for the negative bias temperature instability (NBTI) of PMOS under both short term and long term operation. Based on the reaction-diffusion (R-D) mechanism, this model accurately captures the dependence of NBTI on the oxide thickness (tox), the diffusing species (H or H2) and other key transistor and design parameters. In addition, a closed form expression was derived for the threshold voltage change (DeltaVth ) under multiple cycle dynamic operation. Model accuracy and efficiency were verified with 90-nm experimental and simulation data. The impact of NBTI was further investigated on representative digital circuits
431 citations
"Statistical analysis of BTI in the ..." refers background in this paper
...Transistor aging arises from different sources, however, (Negative/Positive) Bias Temperature Instability (BTI) is considered as the dominant factor [3]....
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TL;DR: This paper develops a hierarchical framework for analyzing the impact of NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity, and proposes an efficient method to predict the degradation of circuit speed over a long period of time.
Abstract: Negative-bias-temperature instability (NBTI) has become the primary limiting factor of circuit life time. In this paper, we develop a hierarchical framework for analyzing the impact of NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity. Given a circuit topology and input switching activity, we propose an efficient method to predict the degradation of circuit speed over a long period of time. The effectiveness of our method is comprehensively demonstrated with the International Symposium on Circuits and Systems (ISCAS) benchmarks and a 65-nm industrial design. Furthermore, we extract the following key design insights for reliable circuit design under NBTI effect, including: 1) During dynamic operation, NBTI-induced degradation is relatively insensitive to supply voltage, but strongly dependent on temperature; 2) There is an optimum supply voltage that leads to the minimum of circuit performance degradation; circuit degradation rate actually goes up if supply voltage is lower than the optimum value; 3) Circuit performance degradation due to NBTI is highly sensitive to input vectors. The difference in delay degradation is up to 5× for various static and dynamic operations. Finally, we examine the interaction between NBTI effect, and process and design uncertainty in realistic conditions.
297 citations
"Statistical analysis of BTI in the ..." refers background or methods in this paper
...The first two components of the Equation (15) show the sensitivity of delay at time = 0 (ΔD0) to the gate length variation and the next two components relate the sensitivity of the BTI-induced delay degradation (ΔDBTI(t)) to the gate length variation....
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...To keep track of the spatial correlations we apply Principal Component Analysis (PCA) to map the correlated variables (e.g. ΔL) to a new set whose elements are mutually independent (orthogonal)....
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...Among them, process variation and transistor aging as well as high temperature and voltage droop profiles (variations) over the die are major threats [1][2]....
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...Note, PCs have standard normal distribution and are same for all correlated variables....
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