Statistical modeling of device mismatch for analog MOS integrated circuits
TL;DR: A generalized parameter-level statistical model, called statistical MOS (SMOS), capable of generating statistically significant model decks from intra- and inter-die parameter statistics is described, and Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device separation distance and device area.
Abstract: A generalized parameter-level statistical model, called statistical MOS (SMOS), capable of generating statistically significant model decks from intra- and inter-die parameter statistics is described. Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device separation distance and device area. Using a Monte Carlo approach to parameter sampling, circuit output means and standard deviations can be simulated. Incorporated in a CAD environment, these modeling algorithms will provide the analog circuit designer with a method to determine the effect of both circuit layout and device sizing on circuit output variance. Test chips have been fabricated from two different fabrication processes to extract statistical information required by the model. Experimental and simulation results for two analog subcircuits are compared to verify the statistical modeling algorithms. >
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TL;DR: This survey attempts to outline some of this recent work on analog testing, ranging from tools for simulation-based test set development and optimization to built-in self-test (BIST) circuitry.
Abstract: Traditionally, work on analog testing has focused on diagnosing faults in board designs. Recently, with increasing levels of integration, not just diagnosing faults, but distinguishing between faulty and good circuits has become a problem. Analog blocks embedded in digital systems may not easily be separately testable. Consequently, many papers have been recently written proposing techniques to reduce the burden of testing analog and mined-signal circuits. This survey attempts to outline some of this recent work, ranging from tools for simulation-based test set development and optimization to built-in self-test (BIST) circuitry.
282 citations
Cites background from "Statistical modeling of device mism..."
...as a function of device area and spacing [30], [32], [33]....
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...In order to characterize global parametric variations, a set of independent factors is usually identified that explain lot-tolot, wafer-to-wafer, and die-to-die variations in a process, often by principal components methods [30], [31]....
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TL;DR: A large-scale monolithic silicon nanophotonic phased array on a chip creates and dynamically steers a high-resolution optical beam in free space, enabling emerging applications in sensing, imaging, and communication.
Abstract: A large-scale monolithic silicon nanophotonic phased array on a chip creates and dynamically steers a high-resolution optical beam in free space, enabling emerging applications in sensing, imaging, and communication. The scalable architecture leverages sub-array structure, mitigating the impact of process variation on the phased array performance. In addition, sharing control electronics among multiple optical modulators in the scalable architecture reduces the number of digital-to-analog converters (DACs) required for an $N^{2}$ array from $\mathcal {O}(N^{2})$ to $\mathcal {O}(N)$ , allowing a small silicon footprint. An optical phased array for 1550-nm wavelength with 1024 uniformly spaced optical grating antennas, 1192 optical variable phase shifters, and 168 optical variable attenuators is integrated into a 5.7 mm $\times$ 6.4 mm chip in a commercial 180-nm silicon-on-insulator RF CMOS technology. The control signals for the optical variable phase shifters and attenuators are provided by 136 DACs with 14-bit nonuniform resolution using 2.5-V input-output transistors. The implemented phased array can create 0.03° narrow optical beams that can be steered unambiguously within ±22.5°.
217 citations
Cites background from "Statistical modeling of device mism..."
...Device mismatch due to process non-uniformity [22]–[24] is a fundamental limiting factor preventing the realization of a monolithically integrated large-scale optical phased array with a conventional architecture....
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TL;DR: In this paper, a unified, comprehensive approach to the design of continuous-time and discrete-time cellular neural networks (CNNs) using CMOS current-mode analog techniques is presented.
Abstract: A unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNNs) using CMOS current-mode analog techniques is presented. The net input signals are currents instead of voltages, which avoids the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploiting current mirror properties for the efficient implementation of both linear and nonlinear analog operators. Basic design issues, the influence of nonidealities and advanced circuit design issues, and design for manufacturability considerations associated with statistical analysis are discussed. Experimental results are given for three prototypes designed for 1.6- mu m n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. >
192 citations
Cites background from "Statistical modeling of device mism..."
...However, a more restrictive bound exists due to MOS transistor mismatch [21], [ 24 ] and Early voltage (VA) degradation with channel length....
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TL;DR: Algorithms for fault-driven test set selection are presented based on an analysis of the types of tests needed for different types of faults, and a major reduction in testing time should come from reducing the number of specification tests that need to be performed.
Abstract: Analog testing is a difficult task without a clearcut methodology. Analog circuits are tested for satisfying their specifications, not for faults. Given the high cost of testing analog specifications, it is proposed that tests for analog circuits should be designed to detect faults. Therefore analog fault modeling is discussed. Based on an analysis of the types of tests needed for different types of faults, algorithms for fault-driven test set selection are presented. A major reduction in testing time should come from reducing the number of specification tests that need to be performed. Hence algorithms are presented for minimizing specification testing time. After specification testing time is minimized, the resulting test sets are supplemented with some simple, possibly non-specification, tests to achieve 100% fault coverage. Examples indicate that fault-driven test set development can lead to drastic reductions in production testing time. >
182 citations
Book•
11 Dec 2012TL;DR: Analog-to-Digital Conversion presents an overview of the state-of-the-art in this field and focuses on issues of optimizing accuracy and speed while reducing the power level, which makes it a reference for the experienced engineer.
Abstract: The design of an analog-to-digital converter or digital-to-analog converter is one of the most fascinating tasks in micro-electronics. In a converter the analog world with all its intricacies meets the realm of the formal digital abstraction. Both disciplines must be understood for an optimum conversion solution. In a converter also system challenges meet technology opportunities. Modern systems rely on analog-to-digital converters as an essential part of the complex chain to access the physical world. And processors need the ultimate performance of digital-to-analog converters to present the results of their complex algorithms. The same progress in CMOS technology that enables these VLSI digital systems creates new challenges for analog-to-digital converters: lower signal swings, less power and variability issues. Last but not least, the analog-to-digital converter must follow the cost reduction trend. These changing boundary conditions require micro-electronics engineers to consider their design choices for every new design. Analog-to-Digital Conversion discusses the different analog-to-digital conversion principles: sampling, quantization, reference generation, nyquist architectures and sigma-delta modulation. Analog-to-Digital Conversion presents an overview of the state-of-the-art in this field and focuses on issues of optimizing accuracy and speed while reducing the power level. A lot of background knowledge and practical tips complement the discussion of basic principles, which makes Analog-to-Digital Conversion also a reference for the experienced engineer.
139 citations
References
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TL;DR: In this paper, the matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured, and the matching results have been verified by measurements and calculations on several basic circuits.
Abstract: The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several basic circuits. >
3,121 citations
TL;DR: In this paper, a characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data and the physical causes of mismatch are discussed in detail for both p- and n-channel devices.
Abstract: A characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data. The physical causes of mismatch are discussed in detail for both p- and n-channel devices. Statistical methods are used to develop analytical models that relate the mismatch to the device dimensions. It is shown that these models are valid for small-geometry devices only. Extensive experimental data from a 3-/spl mu/m CMOS process are used to verify the models. The application of the transistor matching studies to the design of a high-performance digital-to-analog converter (DAC) is discussed. A circuit design methodology is presented that highlights the close interaction between the circuit yield and the matching accuracy of devices. It has been possible to achieve a circuit yield of greater than 97% as a result of the knowledge generated regarding the matching behavior of transistors and due to the systematic design approach.
707 citations
"Statistical modeling of device mism..." refers background in this paper
...Lakshmikumar et al. [ 2 ] advanced this work by separating the area dependence of transistor mismatch into two separate components: the standard deviations of the current factor and the threshold voltage....
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Book•
01 Oct 1988
TL;DR: In this paper, principal component analysis relationships between matrices common practical components proportional covariance matrices partial common components and common space analysis how different are several covariance matrix? numerical methods.
Abstract: Preliminaries principal component analysis relationships between matrices common practical components proportional covariance matrices partial common components and common space analysis how different are several covariance matrices? numerical methods. Appendices: spectral decomposition of symmetric matrices some results from matrix algebra a fortran program for the fg algorithm.
564 citations
"Statistical modeling of device mism..." refers methods in this paper
...The method employed in this study to account for parameter correlations during the calculation of model decks is called the principal component analysis (PCA) [ 20 ]-[22]....
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Book•
14 Mar 1979
TL;DR: Explains fundamental techniques of classical univariate and multivariate statistical analysis and usage of packaged statistical programs, progressing from background material through exploratory techniques to more complicated specialized analyses.
Abstract: Explains fundamental techniques of classical univariate and multivariate statistical analysis and usage of packaged statistical programs, progressing from background material through exploratory techniques to more complicated specialized analyses.
561 citations
"Statistical modeling of device mism..." refers methods in this paper
...The method employed in this study to account for parameter correlations during the calculation of model decks is called the principal component analysis (PCA) [20]-[ 22 ]....
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TL;DR: The Berkeley short-channel IGFET model (BSIM) as discussed by the authors is an accurate and computationally efficient MOS transistor model, and its associated characterization facility for advanced integrated-circuit design is described.
Abstract: The Berkeley short-channel IGFET model (BSIM), an accurate and computationally efficient MOS transistor model, and its associated characterization facility for advanced integrated-circuit design are described. Both the strong-inversion and weak-inversion components of the drain current expression are included. In order to speed up the circuit-simulation execution time, the dependence of the drain current on the substrate bias has been modeled with a numerical approximation. This approximation also simplifies the transistor terminal-charge expressions. The charge model was derived from its drain-current counterpart to preserve consistency of device physics. Charge conservation is guaranteed in this model.
560 citations