Statistical study of the effect of process variations on nano-scale CMOS circuits with scaling
01 Dec 2010-pp 1-4
TL;DR: In this paper, the effect of the variation of process parameters on the performance of a voltage controlled oscillator (VCO) and an inverter with technology scaling is studied. And the spread in performances is shown to be Gaussian in nature.
Abstract: In this paper, we study the effect of the variation of process parameters on the performance of a voltage controlled oscillator (VCO) and an inverter with technology scaling. The spread in performances is shown to be Gaussian in nature, considering the fact that the distributions of process parameters are also Gaussian in nature. The spreads in performances increase with technology scaling. These have been verified through HPSICE simulation results.
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Book•
22 Aug 1997
TL;DR: Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.
Abstract: The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.
2,724 citations
Book•
01 Jan 1987
392 citations
"Statistical study of the effect of ..." refers background in this paper
...These delay parameters are found to depend on the oxide thickness tox, channel length L and the threshold voltage Vt of the NMOS and PMOS transistors [11]....
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TL;DR: A new generation of predictive technology model (PTM) is developed, covering emerging physical effects and alternative structures, based on physical models and early stage silicon data, and correctly captures process sensitivities in the nanometer regime.
Abstract: A predictive MOSFET model is critical for early circuit design research. In this work, a new generation of Predictive Technology Model (PTM) is developed, covering emerging physical effects and alternative structures, such as the double-gate device (i.e., FinFET). Based on physical models and early stage silicon data, PTM of bulk and double-gate devices are successfully generated from 130nm to 32nm technology nodes, with effective channel length down to 13nm. By tuning only ten primary parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified with published silicon data: the error of the current is below 10p for both NMOS and PMOS. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. PTM is available online at http://www.eas.asu.edu/~ptm.
385 citations
"Statistical study of the effect of ..." refers methods in this paper
...At first a nominal circuit is designed for a typical value of the delay parameter using 32nm, 45 nm and 90 nm technology nodes [12]....
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18 Sep 2009
TL;DR: A survey of the evolution of figure of merit for analog-to-digital converters and factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects are presented.
Abstract: As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic effects limiting matching accuracy, electromigration effects limiting conductor lifetime, leakage and mobility effects limiting device performance, and chip power dissipation limits driving individual circuits to be more energy-efficient. The lack of analog design and simulation tools available to address these problems has become the focus of a significant effort with the electronic design automation industry. Postlayout simulation tools are not useful during the design phase, while technology computer-aided design physical simulation tools are slow and not in common use by analog circuit designers. In the nanoscale era of analog CMOS design, an understanding of the physical factors affecting circuit reliability and performance, as well as methods of mitigating or overcoming them, is becoming increasingly important. The first part of the paper presents factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects. Several reliability effects are discussed, including physical design limitations projected for future downscaling. In some cases, it may be helpful to exceed foundry-specified drain-source voltage limits by a few hundred millivolts. Models are presented for achieving this, which include the dependence on the shape of the output waveform. The condition Vsb > 0 is required for cascode circuit configurations. The role of other terminal voltages is discussed, as Vsb > 0 increases both hot and cold carrier damage effects in highly scaled devices. The second part of the paper focuses on trends in device characteristics and how they influence the design of nanoscale analog CMOS circuits. A number of circuit design techniques employed to address the major nonidealities of nanoscale CMOS technologies are discussed. Examples include techniques for establishing on-chip accurate and temperature-insensitive bias currents, digital calibration of analog circuits, and the design of regulator and high-voltage circuits. Achieving high energy efficiency in ICs capable of accommodating 109 devices is becoming critically important. This paper also presents a survey of the evolution of figure of merit for analog-to-digital converters.
202 citations
"Statistical study of the effect of ..." refers background in this paper
...In particular, the process variability in the device and interconnect parameters has become one of the severe bottlenecks in analog/digital circuit designs in nano-scale technologies [2], [3]....
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