Steady state evaluation of distributed secondary frequency control strategies for microgrids in the presence of clock drifts
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Citations
On the Secondary Control Architectures of AC Microgrids: An Overview
Robustness of Distributed Averaging Control in Power Systems: Time Delays & Dynamic Communication Topology
Risk-Averse Model Predictive Operation Control of Islanded Microgrids
Analysis of the Effect of Clock Drifts on Frequency Regulation and Power Sharing in Inverter-Based Islanded Microgrids
Risk-Averse Model Predictive Operation Control of Islanded Microgrids.
References
Power System Stability and Control
Algebraic Graph Theory
Power Generation, Operation, and Control
Control of Power Converters in AC Microgrids
Related Papers (5)
Frequently Asked Questions (20)
Q2. What are the future works in "Steady state evaluation of distributed secondary frequency control strategies for microgrids in the presence of clock drifts*" ?
Future work will address tuning of the different approaches for comparing their dynamic behaviour and to provide a stability proof for the proposed control approach.
Q3. How can a distributed secondary control be used?
Sufficient conditions for zero steady state frequency deviation and power sharing for distributed secondary frequency control approaches have been derived.
Q4. What is the simplest way to reduce the network?
Using Kron-reduction [18], the original network containing passive nodes is reduced to a lower dimensional network that contains only nodes where grid forming units, i.e., grid forming inverters or rotating generators, are connected.
Q5. How is the measured power Pmi R obtained?
The measured active power Pmi ∈ R is obtained by filtering the power output Pi in (1) by a first order low pass filter with time constant τi ∈ R>0.
Q6. What is the standard approach for frequency secondary control?
A standard approach for frequency secondary control is to measure the frequency at a single bus bar where an accurate frequency measurement can be realised.
Q7. What is the steady state frequency error?
The steady state frequency error also goes to zero after a change in active power at t = 30 s occurs (see the bus bar frequency).
Q8. What is the generalised representation of a distributed secondary control scheme?
A generalised representation of a consensus based distributed secondary frequency control scheme explicitly considering clock drifts is(1 + µi)ξ̇i = − ( bi(ω̄i − ω d)+ci ∑j∈JGi aij(ω̄i − ω̄j) + di∑j∈JGi aij(ξi − ξj)), (4)where bi ∈ R is called pinning gain and ci ∈ R as well as di ∈ R are controller gains.
Q9. How can a distributed frequency secondary control be achieved?
In steady state, power sharing can be achieved by using a distributed frequency secondary control that is parametrized as described in Section IV-C.
Q10. What is the condition for the controller?
The power sharing condition (13) for the controller (22)with Bµ = 0J×J is given by (B+ (C+D)L ) F1Jω d + γDLkX1J = 0J , (25)whereF = 1 T J D −1 B1J1T J D−1B1J+1TJ D −1CLµ1J (IJ + µ)− IJ . (26)The condition (25) is satisfied if D−1C = −IJ , which in turn satisfies Lemma 3.
Q11. How can a droop control model be used?
As has been shown in [15], clock drifts can be incorporated in the model of a grid-forming inverter by introducing a (constant) unknown scaling factor in the model.
Q12. What is the internal frequency of the ith unit?
(2c)where µi ∈ R, is the clock drift factor, ωi ∈ R is the actual electrical frequency and ω̄i ∈ R is the internal frequency of the ith unit.
Q13. What is the purpose of this paper?
Future work will address tuning of the different approaches for comparing their dynamic behaviour and to provide a stability proof for the proposed control approach.
Q14. What is the common approach for controlling clock drifts?
Usually in this control scheme, clock drifts are addressed using an accurate central frequency measurement with µc = 0 and hence, ω̄c = ωc.
Q15. What is the frequency error at t = 10 s?
As the controller is enabled at t = 10 s, the error reduces to zero and the frequency is restored to 50 Hz (see magnified plot for frequency).
Q16. What is the effect of the central controller?
The central controller (3) as per Fig. 3a has the capability to address clock drifts due to the presence of an accurate frequency measurement at the bus bar.
Q17. How can different control strategies be implemented?
By parametrising (4), different control strategies can be implemented, e.g., [10], [7] or a controller similar to the one described by [9].
Q18. What is the theoretical result of the steady state analysis in Section IV-C?
the theoretical results from the steady state analysis in Section IV-C could be reproduced, as a zero steady state frequency error as well as power sharing is achieved
Q19. What is the corresponding proof for Lemma 1?
supposing that the system (5) admits a synchronised motion, condition (8) in Lemma 1 reduces to1 T JD −1 Bµ1J = 0. (19)The clock drift factors µi for i ∈ J are uncertain.
Q20. What is the dynamic of the ith unit equipped with frequency droopcontrol?
the dynamics of the ith unit equipped with frequency droopcontrol is given by(1 + µi)δ̇i = (1 + µi)ωi = ω̄i, (2a)= ωd − ki(P m i − P d i ) + ξi, (2b)(1 + µi)τiṖ m i = −P m i +