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Journal ArticleDOI

Strained Silicon Nanowire Transistors With Germanium Source and Drain Stressors

TL;DR: In this paper, pure germanium (Ge) source/drain (S/D) stressors on the ultranarrow or ultrathin Si S/D regions of nanowire FETs with gate lengths down to 5 nm were demonstrated.
Abstract: We report the first demonstration of pure germanium (Ge) source/drain (S/D) stressors on the ultranarrow or ultrathin Si S/D regions of nanowire FETs with gate lengths down to 5 nm. Ge S/D compressively strains the channel to provide up to ~ 100% I Dsat enhancement. We also introduce a novel Melt-Enhanced Dopant diffusion and activation technique to form fully embedded Si0.15Ge0.85 S/D stressors in nanowire FETs, further boosting the channel strain and achieving ~ 125% I Dsat enhancement.
Citations
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Patent
23 Mar 2011
TL;DR: In this article, techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided.
Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

64 citations

Journal ArticleDOI
TL;DR: In this article, the effects of strain-induced band splitting and band warping on the modification of the average conductivity effective mass and carrier scattering rates were evaluated using a classification scheme based on carrier confinement type (electrostatic and spatial) and the degrees of freedom of the mobile carriers.
Abstract: Using a classification scheme based on carrier confinement type (electrostatic and spatial) and the degrees of freedom of the mobile carriers (3DOF, 2DOF, and 1DOF), strain effects on 3DOF to 1DOF silicon logic devices are compared from quantum confinement and device geometry perspectives. For these varied device geometries and types, the effects of strain-induced band splitting and band warping on the modification of the average conductivity effective mass and carrier scattering rates are evaluated. It is shown that the beneficial effects of strain-induced band splitting are the most effective for devices with little or no initial band splitting and become less so for devices with already large built-in band splitting. For these devices with large splitting energy, the potential for strain-induced carrier conductivity mass reduction through repopulation of lower energy bands and the suppression of optical intervalley phonon scattering are limited. On the other hand, for all devices without spatial confin...

54 citations

Journal ArticleDOI
TL;DR: In this article, germanium nanowires with different cross-sectional areas are considered as the channel of a cylindrical surrounding gate field effect transistors (CSG-FETs) and the electronic properties of them are calculated through the density functional method and Slater-Koster (SK) tight binding model.

19 citations

Patent
Glenn A. Glass1, Anand S. Murthy1, Tahir Ghani1, Ying Pang1, Nabil G. Mistkawi1 
21 Mar 2014
TL;DR: In this article, techniques for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to reduce contact resistance have been discussed, and the techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive ge-rich materials.
Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm −3 .

16 citations

Journal ArticleDOI
TL;DR: In this paper, an analytical model of the threshold voltage and drain current for gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field effect transistors (MOSFETs) was proposed.
Abstract: Apart from excellent electrostatic capability and immunity to short-channel effects, the performance of gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field-effect transistors (MOSFETs) can be further enhanced by incorporating strain. Owing to the technological importance of strained GAA (S-GAA) NW MOSFETs in modern electronics, we have proposed an analytical model of the threshold voltage and drain current for S-GAA NW MOSFETs taking into account the appreciable contributions of source (S) and drain (D) series resistances in the nanometer regime, along with quantum mechanical effect. We have focused on the elliptical cross section of the device as is necessary to consider the fabrication imperfections which give rise to such cross section, rather than an ideal circular structure. Incorporating S/D series resistance in the model of drain current demands for algorithms based on multi-iterative technique, which has been proposed in this paper for analyzing the impact of strain, NW width, aspect ratio and so on, on the performance of S-GAA NW devices with emphasis on CMOS digital circuits. Based on our proposed methodology, we have also investigated the scope of using high-k dielectric materials and metal gate in S-GAA NW structures.

13 citations

References
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Journal ArticleDOI
TL;DR: The transition from 2D to 3D growth of Ge on Si(001) has been investigated with scanning tunneling microscope and a metastable 3D cluster phase with well-defined structure and shape is found.
Abstract: The transition from 2D to 3D growth of Ge on Si(001) has been investigated with scanning tunneling microscopy. A metastable 3D cluster phase with well-defined structure and shape is found. The clusters have a {105} facet structure. Results suggest that these clusters define the kinetic path for formation of ``macroscopic'' Ge islands.

1,226 citations

Journal ArticleDOI
Massimo V. Fischetti1, Z. Ren, Paul M. Solomon1, Min Yang1, K. Rim1 
TL;DR: In this paper, a six-band k⋅p model has been used to study the mobility of holes in Si inversion layers for different crystal orientations, for both compressive or tensile strain applied to the channel, and for a varying thickness of the Si layer.
Abstract: A six-band k⋅p model has been used to study the mobility of holes in Si inversion layers for different crystal orientations, for both compressive or tensile strain applied to the channel, and for a varying thickness of the Si layer. Scattering assisted by phonons and surface roughness has been accounted for, also comparing a full anisotropic model to an approximated isotropic treatment of the matrix elements. Satisfactory qualitative (and in several cases also quantitative) agreement is found between experimental data and theoretical results for the density and temperature dependence of the mobility for (001) surfaces, as well as for the dependence of the mobility on surface orientation [for the (011) and (111) surfaces]. Both compressive and tensile strain are found to enhance the mobility, while confinement effects result in a reduced hole mobility for a Si thickness ranging from 30 to 3 nm.

490 citations

Journal ArticleDOI
TL;DR: In this article, the authors analyzed the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, s/D geometry-based analytical model, which was validated using three-dimensional device simulations and experimental results.
Abstract: The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node.

353 citations


"Strained Silicon Nanowire Transisto..." refers methods in this paper

  • ...resistances RSD were extracted using the total resistance and extrapolation method reported in [23] (Fig....

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Proceedings ArticleDOI
15 Jun 2004
TL;DR: In this paper, a new nanowire FinFET structure was developed for CMOS device scaling into the sub-10 nm regime, and gate delay of 0.22 and 0.48 ps with excellent sub-threshold characteristics were achieved with very low off leakage cur-rent less than 10 nA/ /spl mu/m.
Abstract: A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage cur-rent less than 10 nA/ /spl mu/m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

292 citations


"Strained Silicon Nanowire Transisto..." refers background in this paper

  • ...to their direct compatibility with conventional CMOS process flow [1]–[5]....

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Journal ArticleDOI
TL;DR: In this article, the authors show that gate-source/drain (G-S/D) underlap can be achieved via large, doable straggle in the S-D fin-extension doping profile.
Abstract: Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.

253 citations


"Strained Silicon Nanowire Transisto..." refers background in this paper

  • ...This improves the electrostatic control of the nanowire channel by the gate in the OFF-state [12]....

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  • ...High-performance transistors and low-operating power transistors have different requirements on the ON- and OFF-state drain currents....

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