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Proceedings ArticleDOI

Structural design of three-dimensionally stacked silicon chips for minimizing their residual stress

01 Nov 2007-pp 1-6
TL;DR: In this article, the authors proposed the optimum stacked structures for minimizing the residual stress based on a finite element analysis when the thickness of the upper and bottom chips are thinned from 100 mum to 30 mum, regardless of the material of a substrate.
Abstract: Since mechanical stress sometimes degrades both electronic functions and reliability of LSI chips, it is very important to control the residual stress in them to assure their highly reliable performance The authors have already found that the local residual stress distribution on the transistor formation surface of LSIs changes significantly depending on their assembly structure In addition, we have found that the dominant structural factors that determine the distribution are the thickness of a chip, thermal expansion coefficient of underfill material and the shape and the relative position of bumps among stacked chips In this study, we proposed the optimum stacked structures for minimizing the residual stress based on a finite element analysis When the thickness of the upper and bottom chips are thinned from 100 mum to 30 mum, the average value of the normal stress increased monotonically regardless of the material of a substrate The rate of the increase of the average value was about 06 MPa/mum when the material of the substrate was silicon, while the rate of the increase was about 20 MPa/mum when the substrate was an organic one On the other hand, the maximum amplitude of the normal stress in the both chips mounted on an organic substrate was decreased to about 0 MPa, while the maximum amplitude of the normal stress in the stacked chips mounted on a Si substrate changed complicatedly Therefore, it can be said that a Si substrate is effective for minimizing the increase of the average vale of the normal stress, while an organic substrate is effective for minimizing the maximum amplitude of the normal stress by thinning of the chip But, it was also found that there was no way to decrease both the average stress and the maximum amplitude of the residual stress at the same time It is very important, therefore, to optimize the structure of each product by considering the most important part of the stress that dominates the electronic performance of the product However, it should be also noted that the thermal residual stress in the whole structure can not be made 0 because there is the difference of material properties among LSI chips, bumps, underfill and substrates Thus, the stress sensitivity of electronic performance and reliability of each chip should be evaluated before this structural design
Citations
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Dissertation
05 Aug 2014
TL;DR: In this article, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process.
Abstract: Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of mechanical loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k dielectric top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. (111) silicon test chips were used to measure the complete threedimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chip die are subjected to relatively large compressive in-plane normal stresses after solder

3 citations


Cites background from "Structural design of three-dimensio..."

  • ...Miura, et al. [63–65] also used (100) chips to study die stresses in dual inline packages....

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  • ...Ueta and Miura [179, 180] have confirmed the presence of stress gradients in flip chip die by placing much smaller piezoresistive test structures between flip chip bumps....

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  • ...Ueta and Miura [179, 180] have performed some initial measurements of this effect by placing 5 sensors elements between a pair of solder balls at the corner of a flip chip die....

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  • ...The chips used the same sensor orientations as the Miura chips, but the doping of the sensor pairs was reversed....

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References
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Journal ArticleDOI
TL;DR: In this paper, a stress analysis program, SIMUS (stress analysis program for multilayer structure) 2D/F, which can analyze the stress state of thin multi-layer structures such as LSI devices throughout their manufacturing process, was used.
Abstract: Deviation in device characteristics due to mechanical stress is investigated experimentally and analytically from the viewpoints of scaling and hot-carrier effects. A stress analysis program, SIMUS (stress analysis program for multilayer structure) 2D/F, which can analyze the stress state of thin multilayer structures such as LSI devices throughout their manufacturing process, was used. In scaled MOS devices, the effect of uniaxial stress is reduced. However, the effect of vertical stress, such as mold stress, becomes a serious problem when the vertical stress causes compressive surface stress. Compressive stress has a serious effect on electron trapping, in SiO/sub 2./ These results provide important guidelines for the manufacture and package design of deep submicrometer devices. >

183 citations

Proceedings ArticleDOI
04 Jun 1990
TL;DR: In this article, external compressive stress longitudinal to the current flow increases the capture rate of hot electrons in SiO2 and that tensile stress has less influence in both NMOS and PMOS.
Abstract: MOS device characteristics were investigated by imposing external mechanical stress on a Si chip and experimental results are physically evaluated using mechanical stress simulation. Deviation of device characteristics due to external stress is strongly dependent on gate length. This is due to a redistribution of stress in the channel by external stress, which is a strong function of length. That is, the shorter the gate length, the smaller the surface stress due to external stress along the channel. Experiments on hot-carrier injection shows that external compressive stress longitudinal to the current flow increases the capture rate of hot electrons in SiO2 and that tensile stress has less influence in both NMOS and PMOS. In deep-submicron devices, the external stress effect tends to be less. This will be favorable for final fabrication like packaging

73 citations


"Structural design of three-dimensio..." refers background in this paper

  • ...Since high stress and strain deform the crystallographic structure of the materials, the electronic functions and reliability of LSI chips may be deteriorated due to the change of band gap of semiconductor or dielectric materials [8]-[11]....

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Journal ArticleDOI

19 citations


"Structural design of three-dimensio..." refers background in this paper

  • ...Three dimensionally stacked structures such as multi-chip modules and multi-chip packages are indispensable for these products in order to increase the assembly density [1][2]....

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Proceedings ArticleDOI
H. Miura1
01 Jan 2003
TL;DR: In this paper, the residual stress in silicon chips encapsulated in plastic packages using Cu-alloy frames was measured using stress sensing chips by varying the combination of structure and material of metallic lead-frames and molding resin.
Abstract: The residual stress in silicon chips encapsulated in plastic packages using Cu-alloy frames was measured using stress sensing chips by varying the combination of structure and material of metallic lead-frames and molding resin because the mechanical reliability such as cracking of silicon chips and the shift of the electronic performance of LSI strongly depends on the stress. Since the adhesion condition between a silicon chip and the Cu-alloy frame was unstable due to the large mismatch in thermal expansion coefficient between them, the residual stress after encapsulation varied from tensile stress to high compressive stress depending on the combination of the packaging materials such as die-bonding paste and molding resin. It was found that the residual stress can be controlled and minimized by using the chip-on-lead (COL) type package because the dielectric film between the Cu-alloy frame and a silicon chip acts as a stress relaxation layer.

10 citations


"Structural design of three-dimensio..." refers background in this paper

  • ...Such a localized high stress or strain may give rise to mechanical fracture such as delamination or cracking of materials [7]....

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  • ...For example, when a compressive stress is applied to a PMOS transistor perpendicularly to the channel, its transconductance (Gm) decreases by about 18% per 100 MPa [7]....

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