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Proceedings ArticleDOI

Structured ASIC Design for Space Systems Applications

05 Mar 2005-pp 1-6
TL;DR: Structured ASICs as mentioned in this paper are designed from an inventoried base masterslice chip design by using generally only a few back-end masking levels to personalize the resulting ASIC function, saving mask costs and shortening lead times per circuit design.
Abstract: As integrated circuit dimensions scale downward the costs of the photolithographic masks used to manufacture microcircuits are becoming prohibitively high. And in today's highly competitive business environment, time to market is increasingly critical. Custom standard-cell ASICs are on the wrong side of these dynamics with their long lead times and the need to build a full mask set per part number. Structured ASICs offer an attractive alternative. Structured ASICs are developed from an inventoried base masterslice chip design by using generally only a few back-end masking levels to personalize the resulting ASIC function, saving mask costs and shortening lead times per circuit design. Structured ASICs strategically fill the trade space between FPGAs and custom ASICs. BAE Systems has developed a radiation hardened structured ASIC product offering for next-generation advanced military and space applications
Citations
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Proceedings ArticleDOI
28 May 2013
TL;DR: In this paper, a 3D-stackable 12×12mm structured ASIC die with 42k interconnects is presented, which is resource compatible with an existing 2D structured ASIC device of the same size.
Abstract: This paper presents a novel 3D structured ASIC platform that lowers the development effort required to deploy 3D integration technologies in cost sensitive, low-volume applications. The key advantage of this structured 3D ASIC architecture, over custom 3D ASICs, is a fixed vertical interconnect pattern that is programmed by a single 2D metal-via mask, allowing individual die levels to be rapidly designed, fabricated, and assembled. The first silicon realization of this architecture is a 3D-stackable 12×12mm structured ASIC die with 42K interconnects, which is resource compatible with an existing 2D structured ASIC device of the same size. 3D die stacks built using this platform are also intended to be a less costly and more flexible replacement for a large 20×20mm monolithically integrated structured ASIC device. This 3D structured ASIC platform was des igned and fabricated in Sandia's 0.35-μm foundry, and high-density front-end-of-line through silicon vias (TSVs) were developed to implement the 3D vertical interconnects1.
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Proceedings ArticleDOI
13 Oct 2003
TL;DR: A new category of devices-known as structured ASICs-is now becoming available, which bridge the gap between FPGAs and ASICs in terms of cost and capabilities, but they also pose challenges to device manufacturers and design tool vendors.
Abstract: There is currently a huge gap between the two main technologies used to implement custom digital integrated circuit (IC) designs. At one end of the spectrum are field programmable gate arrays (FPGAs). These devices have relatively low design costs and short design times, but they also have high per-unit costs and are limited in terms of design size, complexity, and performance. At the other end of the device continuum are application specific integrated circuits (ASICs). These components have exceedingly high design costs and take a long time to develop, but they can support extremely large, complex, and high-performance designs, and they have low per-unit costs in large production runs. A new category of devices-known as structured ASICs-is now becoming available. These devices bridge the gap between FPGAs and ASICs in terms of cost and capabilities, but they also pose challenges to device manufacturers and design tool vendors.

94 citations


"Structured ASIC Design for Space Sy..." refers background in this paper

  • ...Structured ASICs bridge the FPGA–standard cell ASIC gap [1]....

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  • ...They bridge the gap between FPGAs and standard cell ASICs (SC ASICs) in terms of cost and capabilities, as depicted in Figure 1 [1]....

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