Journal ArticleDOI
STT-RAM Cache Hierarchy With Multiretention MTJ Designs
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TLDR
A range of cache hierarchy designs implemented entirely using STT-RAM that deliver optimal power saving and performance, while improving instruction per cycle performance for both two-level and three-level cache hierarchies are proposed.Abstract:
Spin-transfer torque random access memory (STT-RAM) is the most promising candidate to be universal memory due to its good scalability, zero standby power, and radiation hardness Having a cell area only 1/9 to 1/3 that of SRAM, allows for a much larger cache with the same die footprint Such reduction of cell size can significantly shrink the cache array size, leading to significant improvement of overall system performance and power consumption, especially in this multicore era where locality is crucial However, deploying STT-RAM technology in L1 caches is challenging because write operations on STT-RAM are slow and power-consuming In this paper, we propose a range of cache hierarchy designs implemented entirely using STT-RAM that deliver optimal power saving and performance In particular, our designs use STT-RAM cells with various data retention times and write performances, made possible by novel magnetic tunneling junction designs For L1 caches where speed is of utmost importance, we propose a scheme that uses fast STT-RAM cells with reduced data retention time coupled with a dynamic refresh scheme In the dynamic refresh scheme, another emerging technology, memristor, is used as the counter to monitor the data retention of the low-retention STT-RAM, achieving a higher array area efficiency than an SRAM-based counter For lower level caches with relatively larger cache capacities, we propose a design that has partitions of different retention characteristics, and a data migration scheme that moves data between these partitions The experiments show that on the average, our proposed multiretention level STT-RAM cache reduces total energy by as much as 30%–742% compared to previous single retention level STT-RAM caches, while improving instruction per cycle performance for both two-level and three-level cache hierarchiesread more
Citations
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Journal ArticleDOI
Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Xuanyao Fong,Yusung Kim,Rangharajan Venkatesan,Sri Harsha Choday,Anand Raghunathan,Kaushik Roy +5 more
TL;DR: The state of the art in STT-MRAM is discussed, beginning with the device design concepts and challenges, followed by the corresponding bit-cell design solutions suitable for on-chip applications.
Proceedings ArticleDOI
Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems
TL;DR: A real-time flash translation layer (RFTL) scheme to evenly distribute garbage collection time-cost, so as to guarantee a near optimum worst-case response time is proposed by using a new hybrid-level address mapping approach.
Journal ArticleDOI
Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM
TL;DR: A thermal-aware MTJ model is proposed as the basis for thoroughly thermal aware analysis of a 1T1MTJ STT-RAM cell structure, and temperature effect on memory cell access behavior in terms of access latency, energy, and reliability on a 45-nm technology node is investigated.
Journal ArticleDOI
Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications
TL;DR: The memristor and STT-RAM power has been compared with the traditional six-transistor-SRAM-based memory power and potential application in wireless sensor nodes is explored.
Journal ArticleDOI
Hybrid crossbar architecture for a memristor based cache
TL;DR: A new memristor crossbar architecture that is proposed for use in a high density cache design that has less than 10% of the write energy consumption and allows better performance along with lower system power when compared to the STT-MRAM and SRAM caches.
References
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The missing memristor found
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Journal ArticleDOI
Memristor-The missing circuit element
TL;DR: In this article, the memristor is introduced as the fourth basic circuit element and an electromagnetic field interpretation of this relationship in terms of a quasi-static expansion of Maxwell's equations is presented.
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Proceedings ArticleDOI
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
TL;DR: This paper stacks MRAM-based L2 caches directly atop CMPs and compares it against SRAM counterparts in terms of performance and energy, and proposes two architectural techniques: read-preemptive write buffer and SRAM-MRAM hybrid L2 cache.