Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor
TL;DR: In this article, a comparative study between EδDC bulk MOS transistor with gate length Lg = 22nm and a conventional uniformly doped channel (UDC) transistor, with respect to various digital and analogue performances, is presented.
Abstract: Epitaxial delta-doped channel (EδDC) profile is a promising approach for extending the scalability of bulk metal oxide semiconductor (MOS) technology for low-power system-on-chip applications. A comparative study between EδDC bulk MOS transistor with gate length Lg = 22 nm and a conventional uniformly doped channel (UDC) bulk MOS transistor, with respect to various digital and analogue performances, is presented. The study has been performed using Silvaco technology computer-aided design device simulator, calibrated with experimental results. This study reveals that at smaller gate length, EδDC transistor outperforms the UDC transistor with respect to various studied performances. The reduced contribution of the lateral electric field in the channel plays the key role in this regard. Further, the carrier mobility in EδDC transistor is higher compared to UDC transistor. For moderate gate and drain bias, the impact ionisation rate of the carriers for EδDC MOS transistor is lower than that of the UDC transis...
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TL;DR: In this paper, the authors proposed an effective technique to implement a graded channel (GC) nanoscale MOSFET without the need for a separate implantation, which exhibits reduced drain-induced barrier lowering, improved intrinsic gain, cutoff frequency, and maximum oscillation frequency.
Abstract: In this paper, using the charge-plasma concept, we propose an effective technique to implement a graded channel (GC) nanoscale MOSFET without the need for a separate implantation. The characteristics are demonstrated and compared with conventional dopingless, junctionless, and underlap inversion-mode MOSFET. The results show that the proposed GC device exhibits reduced drain-induced barrier lowering, improved intrinsic gain ( ${A} _{V}$ ), cutoff frequency ( ${f} _{T}$ ), and maximum oscillation frequency ( ${f} _{\mathrm{MAX}}$ ). Our approach overcomes the difficulty of creating a narrow GC doping profile and, thus, makes the GC MOSFET more attractive in carrying on with the scaling trend. The possible fabrication process flow of GC-double-gate (DG) FET is also proposed.
42 citations
TL;DR: A systematic procedure for the design of a channel profile of an epitaxial delta doped channel (EδDC) MOS transistor so that the intrinsic gain (Au) is high and the threshold voltage (VT) mismatch is low.
Abstract: In this paper, we present a systematic procedure for the design of a channel profile of an epitaxial delta doped channel ( $\text{E}\delta $ DC) MOS transistor so that the intrinsic gain ( $A_{v}$ ) is high and the threshold voltage ( $V_{T}$ ) mismatch is low. Analytical study shows that a tradeoff relation exists between low $V_{T}$ mismatch and high $A_{V}$ with respect to the thickness of the channel region. Therefore, careful selection of the design parameters is essential in order to have an optimum performance. The performance characteristics of the designed device are subsequently verified through Technology Computer Aided Design simulations. In order to demonstrate the benefits of using optimized $\text{E}\delta $ DC transistor, we compare its performance with that of a reference deeply depleted channel MOS transistor. The performance improvement of using optimized $\text{E}\delta $ DC transistor with respect to the chosen objectives is clearly explained.
7 citations
Cites background from "Study of performance scaling of 22-..."
...The performance scaling of EδDC transistor has been thoroughly studied in [13]....
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01 Sep 2017-Microsystem Technologies-micro-and Nanosystems-information Storage and Processing Systems
TL;DR: A comprehensive analytical and technology computer-aided design (TCAD) simulation study of the effects of variation of temperature on the threshold voltage and sub-threshold slope of an n-type E$$\delta$$δDC MOS transistor in the wide range of 100–500 K.
Abstract: For low power System-on-Chip applications, where cost is a critical factor, recently proposed epitaxial delta doped channel (E
$$\delta$$
DC) structure is a promising alternative architecture within the planar bulk MOS transistor technology due to enhanced electrostatic integrity and reduced threshold voltage variability Sengupta and Pandit (IEEE Trans Electron Dev 63(2):551–557, 2016). In this paper we present a comprehensive analytical and technology computer-aided design (TCAD) simulation study of the effects of variation of temperature on the threshold voltage and sub-threshold slope of an n-type E
$$\delta$$
DC MOS transistor in the wide range of 100–500 K. We assume Berkeley Short Channel IGFET Model (BSIM) framework for the analytical model. The quantum correction of the threshold voltage is considered while developing the analytical model. The amount of short channel effects at low and high drain bias increase linearly with temperature above 300 K and reduces with reduction in temperature below 300 K. The sub-threshold slope varies linearly with temperature. Another important contribution of this work is that, we also discuss two strategies for reducing the effect of temperature variations on the threshold voltage at the device design level and at the circuit design level.
5 citations
TL;DR: In this paper, a physics-based small signal model of drain current local variability due to random discrete dopant effect for an n-type epitaxial delta-doped (E $\delta$ DC) MOS transistor is presented.
Abstract: In this paper, we present a physics-based small signal model of drain current local variability due to random discrete dopant effect for an n-type epitaxial delta-doped (E $\delta$ DC) MOS transistor. Based on the analogy with flicker noise phenomenon, the concept of inversion charge fluctuation with correlated mobility fluctuation (MF) is utilized. The correlated MF has two components. One is due to Coulomb impurity scattering of the inversion carriers with the ionized impurity atoms. The second component is due to the fluctuation of the effective electric field that results in fluctuation of the inversion charges. The model is verified with calibrated technology computer-aided design simulation results for all bias regions for five different device geometries and three different operative temperatures. Impact of channel engineering for reduction of the drain current local variability is studied in detail.
3 citations
Cites background from "Study of performance scaling of 22-..."
...The scaling, substrate bias and VT mismatch performances of this device are reported in [3], [11], and [12]....
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References
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Book•
IBM1
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.
2,680 citations
Book•
01 Jan 1984
TL;DR: The history of numerical device modeling can be traced back to the early 1970s as mentioned in this paper, when the basic Semiconductor Equations were defined and the goal of modeling was to identify the most fundamental properties of numerical devices.
Abstract: 1. Introduction.- 1.1 The Goal of Modeling.- 1.2 The History of Numerical Device Modeling.- 1.3 References.- 2. Some Fundamental Properties.- 2.1 Poisson's Equation.- 2.2 Continuity Equations.- 2.3 Carrier Transport Equations.- 2.4 Carrier Concentrations.- 2.5 Heat Flow Equation.- 2.6 The Basic Semiconductor Equations.- 2.7 References.- 3. Proeess Modeling.- 3.1 Ion Implantation.- 3.2 Diffusion.- 3.3 Oxidation.- 3.4 References.- 4. The Physical Parameters.- 4.1 Carrier Mobility Modeling.- 4.2 Carrier Generation-Recombination Modeling.- 4.3 Thermal Conductivity Modeling.- 4.4 Thermal Generation Modeling.- 4.5 References.- 5. Analytical Investigations About the Basic Semiconductor Equations.- 5.1 Domain and Boundary Conditions.- 5.2 Dependent Variables.- 5.3 The Existence of Solutions.- 5.4 Uniqueness or Non-Uniqueness of Solutions.- 5.5 Sealing.- 5.6 The Singular Perturbation Approach.- 5.7 Referenees.- 6. The Diseretization of the Basic Semiconductor Equations.- 6.1 Finite Differences.- 6.2 Finite Boxes.- 6.3 Finite Elements.- 6.4 The Transient Problem.- 6.5 Designing a Mesh.- 6.6 Referenees.- 7. The Solution of Systems of Nonlinear Algebraic Equations.- 7.1 Newton's Method and Extensions.- 7.2 Iterative Methods.- 7.3 Referenees.- 8. The Solution of Sparse Systems of Linear Equations.- 8.1 Direct Methods.- 8.2 Ordering Methods.- 8.3 Relaxation Methods.- 8.4 Alternating Direction Methods.- 8.5 Strongly Implicit Methods.- 8.6 Convergence Acceleration of Iterative Methods.- 8.7 Referenees.- 9. A Glimpse on Results.- 9.1 Breakdown Phenomena in MOSFET's.- 9.2 The Rate Effect in Thyristors.- 9.3 Referenees.- Author Index.- Table Index.
2,550 citations
"Study of performance scaling of 22-..." refers methods in this paper
...The impact ionisation rate, which is based upon Selberherr’s model (Selberherr, 1984), is written as (Pandit et al., 2014; Saha, 1996) Isub IDS ¼ Ai Bi ltEm exp BiEm (1) where Ai and Bi are ionisation constants and Em is maximum electric field in the velocity saturation region and is defined as Em…...
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TL;DR: A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields.
Abstract: A semiempirical model for carrier mobility in silicon inversion layers is presented. The model, strongly oriented to CAD (computer-aided design) applications, is suitable for two-dimensional numerical simulations of nonplanar devices. A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields, channel impurity concentrations of between 5*10/sup 14/ cm/sup -3/ and 10/sup 17/ cm/sup -3/ for the acceptor density of states and 6*10/sup 14/ cm/sup -3/ and 3*10/sup 17/ cm/sup -3/ for the donor density of states; and temperatures between 200 K and 460 K. Best-fit model parameters are extracted by comparing the calculated drain conductance with a very large set of experimental data points. >
697 citations
"Study of performance scaling of 22-..." refers methods in this paper
...In TCAD simulations, this is considered through the use of concentration-dependent mobility model (Lombardi et al., 1988), which shows that the carrier mobility increases with reduction of doping concentration in the channel region....
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01 Jan 2016
244 citations
"Study of performance scaling of 22-..." refers background in this paper
...With the drain voltage VDS sufficiently higher than the drain-to-source saturation voltage VDSsat, the maximum electric field in the velocity saturation region near the drain end becomes so high that impact ionisation phenomenon happens (Taur & Ning, 1998)....
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TL;DR: In this article, a detailed three-dimensional (3D) statistical "atomistic" simulation study of fluctuation-resistant sub 0.1/spl mu/m MOSFET architectures with epitaxial channels and delta doping is presented.
Abstract: A detailed three-dimensional (3-D) statistical "atomistic" simulation study of fluctuation-resistant sub 0.1-/spl mu/m MOSFET architectures with epitaxial channels and delta doping is presented. The need for enhancing the fluctuation resistance of the sub-0.1-/spl mu/m generation transistors is highlighted by presenting summarized results from atomistic simulations of a wide range of conventional devices with uniformly doped channels. According to our atomistic results, the doping concentration dependence of the random dopant-induced threshold voltage fluctuations in conventional devices is stronger than the analytically predicted fourth-root dependence. As a result of this, the scaling of such devices will be restricted by the "intrinsic" random dopant-induced fluctuations earlier than anticipated. Our atomistic simulations confirm that the introduction of a thin epitaxial layer in the MOSFET's channel can efficiently suppress the random dopant-induced threshold voltage fluctuations in sub-0.1-/spl mu/m devices. For the first time, we observe an "anomalous" reduction in the threshold voltage fluctuations with an increase in the doping concentration behind the epitaxial channel, which we attribute to screening effects. Also, for the first time we study the effect of a delta doping, positioned behind the epitaxial layer, on the intrinsic threshold voltage fluctuations. Above a certain thickness of epitaxial layer, we observe a pronounced anomalous decrease in the threshold voltage fluctuation with the increase of the delta doping. This phenomenon, which is also associated with screening, enhances the importance of the delta doping in the design of properly scaled fluctuation-resistant sub-0.1-/spl mu/m MOSFET's.
176 citations
"Study of performance scaling of 22-..." refers background in this paper
...…Journal of Electronics, 2015 Vol. 102, No. 6, 967–981, http://dx.doi.org/10.1080/00207217.2014.945194 © 2014 Taylor & Francis EδDC MOS transistor for reduction of threshold voltage variations due to random dopant fluctuation effect is discussed in Asenov and Saini (1999)....
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