Study of Subharmonically Injection-Locked PLLs
TL;DR: A complete analysis on subharmonically injection-locked PLLs develops fundamental theory for subharmonic locking phenomenon, which explains the noise shaping phenomenon, locking range and behavior, PVT tolerance, and pseudo locking issue.
Abstract: A complete analysis on subharmonically injection-locked PLLs develops fundamental theory for subharmonic locking phenomenon. It explains the noise shaping phenomenon, locking range and behavior, PVT tolerance, and pseudo locking issue. All of the analyses are verified by real chip measurements. Two 20-GHz PLLs based on the proposed theory are designed and fabricated in 90-nm CMOS technology to demonstrate the superiority and robustness of this technique. The first chip aims at low-noise/low-power/high-divide-ratio design, achieving 149-fs rms jitter (integrated from 100 Hz to 1 GHz) while consuming 38 mW from a 1.3-V supply. The second prototype shoots for the lowest noise performance, presenting 85-fs rms jitter (the same integration interval) with a power dissipation of 105 mW. The jitter generation (from 50 kHz to 80 MHz) measures 48 fs, which is at least twice as small as that of any other known circuits.
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TL;DR: Two ultra-high-speed SerDes dedicated for PAM4 and NRZ data are presented, providing prospective design examples for next-generation 400 GbE.
Abstract: This paper presents two ultra-high-speed SerDes dedicated for PAM4 and NRZ data The PAM4 TX incorporates an output driver with 3-tap FFE and adjustable weighting to deliver clean outputs at 4 levels, and the PAM4 RX employs a purely linear full-rate CDR and CTLE/1-tap DFE combination to recover and demultiplex the data NRZ TX includes a tree-structure MUX with built-in PLL and phase aligner NRZ RX adopts linear PD with special vernier technique to handle the 56 Gb/s input data All chips have been verified in silicon with reasonable performance, providing prospective design examples for next-generation 400 GbE
114 citations
Cites background from "Study of Subharmonically Injection-..."
...[12], the PLL provides a pure clock with rms jitter around...
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TL;DR: In this paper, a phase-locked loop (PLL) reference-spur reduction design technique exploiting a sub-sampling phase detector (SSPD) is presented.
Abstract: This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 μm CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is <; -80 dBc. The PLL consumes 3.8 mW while the in-band phase noise is -121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3psrms.
113 citations
TL;DR: A 21-Gb/s backplane transceiver has been presented that incorporates half-rate topology with purely digital blocks to substantially reduce power consumption and employs analog and decision-feedback equalizers in a full-rate structure to avoid complicated structure.
Abstract: A 21-Gb/s backplane transceiver has been presented. The transmitter incorporates half-rate topology with purely digital blocks to substantially reduce power consumption. The receiver employs analog and decision-feedback equalizers in a full-rate structure to avoid complicated structure. The one-tap decision-feedback equalizer merges the summer and the slicer into the flipflop, shortening the feedback path and speeding up the operation considerably. Fabricated in 65-nm CMOS, the transceiver (excluding clock generating PLL and CDR circuits) delivers 21-Gb/s data (231- 1 PRBS) over 40-cm FR4 channel while consuming 87 mW from a 1.2-V supply.
106 citations
Cites background from "Study of Subharmonically Injection-..."
...(TSPC) latch consumes much less power than its CML counterpart [19]....
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TL;DR: A mm-wave subharmonic injection-locked (SHIL) fractional-N frequency synthesizer for wireless multiband point-to-point backhaul communications and the proposed ILFM chain employs higher-order LC tanks to generate a rippled phase response over a wide frequency range to significantly enhance the locking range and to eliminate expensive mm- wave frequency calibration loops.
Abstract: This paper presents a mm-wave subharmonic injection-locked (SHIL) fractional-N frequency synthesizer for wireless multiband point-to-point backhaul communications. The SHIL synthesizer implements a low-phase-noise 4.5-6.1 GHz PLL and injects its output to a ÷3/÷4 dual-modulus divider followed by an ultra-wideband injection-locked frequency-multiplier (ILFM) chain to achieve excellent phase noise over an ultra-wide frequency tuning range. The proposed ILFM chain employs higher-order LC tanks to generate a rippled phase response around 0 °
over a wide frequency range to significantly enhance the locking range and to eliminate expensive mm-wave frequency calibration loops. Fabricated in a 65 nm CMOS process, the synthesizer prototype measures a continuous output frequency range from 20.6 to 48.2 GHz with frequency resolution of 220 kHz and output phase noise between -107.0 and -113.9 dBc/Hz at 1 MHz offset while consuming 148 mW and occupying 1850 × 1130 μm 2
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94 citations
Cites background or methods from "Study of Subharmonically Injection-..."
...This is because, as long as the ILFM is locked, the output phase noise tracks closely to the input phase noise by dB up to a frequency offset defined by its locking range , where is the ratio of the output frequency to the input frequency, regardless of the ILFM’s own phase noise [13]–[15]....
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...Block diagrams of (a) a fundamental mm-wave PLL and (b) a SHIL PLL using narrowband frequency multipliers [13]....
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TL;DR: A 28 nm CMOS Radar TX that modulates a 79 GHz carrier with a 2 Gsps Pseudo-Noise sequence is proposed that is functional up to 125°C still providing more than +7 dBm output power over the same RF BW.
Abstract: Millimeter-wave sensors perform robust and accurate remote motion sensing. We propose a 28 nm CMOS Radar TX that modulates a 79 GHz carrier with a 2 Gsps Pseudo-Noise sequence. The measured modulated output power at 79 GHz in 4 GHz BW is higher than +11 dBm (27°C), while the spurious emissions are below -20 dBc, fully satisfying the spectral mask regulations. The output RF BW where we can lock the injection-locked LO is 13 GHz. Overall, the TX draws 121 mW from a 0.9 V supply resulting in a record efficiency above 10%. More importantly, the TX is functional up to 125°C still providing more than +7 dBm output power over the same RF BW.
94 citations
Cites background from "Study of Subharmonically Injection-..."
...Sub-harmonic frequency generation is a popular choice in literature [21]–[23]....
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References
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01 Feb 1966
2,440 citations
Additional excerpts
...2016701 vertically separated by dB [2]....
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01 Jun 1946
TL;DR: In this paper, a differential equation is derived which gives the oscillator phase as a function of time, and with the aid of this equation, the transient process of "pull-in" as well as the production of distorted beat note are described in detail.
Abstract: Impression of an external signal upon an oscillator of similar fundamental frequency affects both the instantaneous amplitude and instantaneous frequency. Using the assumption that time constants in the oscillator circuit are small compared to the length of one beat cycle, a differential equation is derived which gives the oscillator phase as a function of time. With the aid of this equation, the transient process of "pull-in" as well as the production of a distorted beat note are described in detail. It is shown that the same equation serves to describe the motion of a pendulum suspended in a viscous fluid inside a rotating container. The whole range of locking phenomena is illustrated with the aid of this simple mechanical model.
1,751 citations
"Study of Subharmonically Injection-..." refers background in this paper
...simply destroys the loop locking? To answer these questions, we must go back to the injection locking theories [11], [12], [17]....
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...7, the lock range of fundamental (full-rate) injection is given by [11], [12]...
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...Indeed, the VCO phase noise can be dramatically reduced by injection locking [11], [12], since the low-noise source would periodically correct the VCO zero crossings....
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TL;DR: In this paper, an identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction, and the behavior of phase-locked oscillators under injection pulling is also formulated.
Abstract: Injection locking characteristics of oscillators are derived and a graphical analysis is presented that describes injection pulling in time and frequency domains. An identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction. The behavior of phase-locked oscillators under injection pulling is also formulated.
1,159 citations
"Study of Subharmonically Injection-..." refers background or methods in this paper
...Indeed, the VCO phase noise can be dramatically reduced by injection locking [11], [12], since the low-noise source would periodically correct the VCO zero crossings....
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...From the derivation in [12], we realize that the created phase is the angle between and (the total current driving the tank), and (the angle between and ) reaches a maximum as and form a right angle....
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...accuracy), since the locking may fail due to the narrow lock range and PVT variations [12], [13]....
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...Following the analysis in [12], we redraw the equivalent half circuit of an injection-locked oscillator in Fig....
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...simply destroys the loop locking? To answer these questions, we must go back to the injection locking theories [11], [12], [17]....
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TL;DR: This paper analyzes typical charge-pump circuits, identifies salient features, and provides equations and graphs for the design engineer.
Abstract: Phase/frequency detectors deliver output in the form of three-state, digital logic. Charge pumps are utilized to convert the timed logic levels into analog quantities for controlling the locked oscillators. This paper analyzes typical charge-pump circuits, identifies salient features, and provides equations and graphs for the design engineer.
894 citations
"Study of Subharmonically Injection-..." refers background in this paper
...This requirement is difficult to achieve because 1) some standards pre-define the bandwidths mandatorily; 2) even with no restriction posed, the loop bandwidth still needs to be kept below approximately one twentieth of the reference frequency in order to ensure stability [5]; 3) a high loop bandwidth allows more noise from the phase and fre-...
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01 Oct 1973
TL;DR: In this article, a differential equation is derived which gives the oscillator phase as a function of time, and with the aid of this equation, the transient process of "pull-in" as well as the production of distorted beat note are described in detail.
Abstract: Impression of an external signal upon an oscillator of similar fundamental frequency affects both the instantaneous amplitude and instantaneous frequency. Using the assumption that time constants in the oscillator circuit are small compared to the length of one beat cycle, a differential equation is derived which gives the oscillator phase as a function of time. With the aid of this equation, the transient process of "pull-in" as well as the production of a distorted beat note are described in detail. It is shown that the same equation serves to describe the motion of a pendulum suspended in a viscous fluid inside a rotating container. The whole range of locking phenomena is illustrated with the aid of this simple mechanical model.
894 citations