Study of substrate induced strained-Si/SiGe channel for optimizing CMOS digital circuit characteristics
01 Dec 2012-pp 1-4
TL;DR: In this article, the authors have analyzed the characteristics of CMOS inverters using a combination of strained-Si p- and conventional-Si n- channel CMOS in the virtual substrate (VS) and have determined that the two conflicting scaling requirements can converge when the Ge content in VS is ∼ 40%.
Abstract: In this work, the prospect of designing CMOS based digital electronic circuits incorporating strained-Si/Si 1−x Ge x MOSFETs is studied. The fundamental drawback in designing CMOS digital circuits is the compulsion of maintaining a larger width of the p-MOS in respect to its n-MOS counterpart. This is due to the fact that the hole and electron mobilities are not equal. The scale factor of the p-MOS transistor, however, depends on whether the circuit is optimized for robustness or high speed; the choice of one obviously compromises the other performance metric. In this context, incorporation of a strained-Si p-MOS in such a circuit is expected to improve the performance in terms of speed as well as noise margin. We have analyzed the characteristics of CMOS inverters using a combination of strained-Si p- and conventional-Si n- channel CMOS inverters for different compositions of Ge in the virtual substrate (VS) and have determined that the two conflicting scaling requirements can converge when the Ge content in VS is ∼ 40%.
Citations
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TL;DR: In this paper, the impact of bias voltage, temperature, LET, and struck position on SET is considered, and the simulation results demonstrate that bias voltage in the range 0.8 to 1.2V greatly influence the amplitude of SET current.
Abstract: Single event transient of a PMOS using strained Silicon-Germanium in a sub-100nm bulk process is studied by 3D TCAD simulation. The impact of bias voltage, temperature, LET, and struck position on SET is considered. Our simulation results demonstrate that bias voltage in the range 0.8 to 1.2V greatly influence the amplitude of SET current. Temperature has a stronger influence on a SiGe channel PMOS than a Si-channel PMOS. Both SET current duration and total collection charge increase as LET increases, and SET current duration and total collection of a SiGe channel PMOS are larger than that of Si channel PMOS. These simulation results are beneficial to the space application of SiGe circuits.
References
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TL;DR: A review of the history and current progress in highmobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field effect transistors (MOSFETs) can be found in this article.
Abstract: This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...
918 citations
TL;DR: In this article, a tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility.
Abstract: Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.
561 citations
TL;DR: In this paper, the authors investigated the dependence of hole mobility in strained Si MOSFETs on substrate Ge content, strained layer thickness, and channel composition, and showed that hole mobility enhancements saturate at virtual substrate compositions of 40% Ge and above, with peak mobility enhancements over twice that of coprocessed bulk Si devices.
Abstract: Strained Si-based metal–oxide–semiconductor field-effect transistors (MOSFETs) are promising candidates for next-generation complementary MOS (CMOS) technology. While electron mobility enhancements in these heterostructures have been thoroughly investigated, hole mobility enhancements have not been explored in as much detail. In this study, we investigate the dependence of hole mobility in strained Si MOSFETs on substrate Ge content, strained layer thickness, and channel composition. We show that hole mobility enhancements saturate at virtual substrate compositions of 40% Ge and above, with peak mobility enhancements over twice that of coprocessed bulk Si devices. These results represent peak hole mobilities above 200cm2/V-S. Furthermore, we demonstrate that hole mobility in strained Si/relaxed Si0.7Ge0.3 heterostructures displays no strong dependence on strained layer thickness, indicating that strain is the primary variable controlling channel mobility in strained Si p-type MOSFETs (p-MOSFETs). We then ...
165 citations
TL;DR: It is shown that a 4-fold improvement in static and dynamic CMOS circuit performance can be achieved by the introduction of strained silicon MOSFETs and the impact of achievable mobility on device design and performance is presented.
Abstract: It is shown that a 4-fold improvement in static and dynamic CMOS circuit performance can be achieved by the introduction of strained silicon MOSFETs. A 2-fold improvement is obtained using pseudomorphic SiGe pMOSFETs in static CMOS. The industry standard compact model BSIM3v3 is able to capture the features of buried channel and surface channel SiGe based MOSFETs for SPICE simulations. TCAD shows that surface channel strained silicon MOSFETs offer better n-channel performance than buried channel devices, while p-channel devices buried up to 4 nm may outperform surface channel pMOSFETs. The impact of achievable mobility on device design and performance is presented.
47 citations
TL;DR: In this paper, the authors compared the performance of single-and dual-surface channel devices fabricated using 15% Ge content SiGe virtual substrates and found that the compromised performance of the dual-channel devices are attributed to greater interface roughness and increased Ge diffusion resulting from the Si/sub 0.7/Ge/sub 1.3/ buried channel layer.
Abstract: Results comparing strained-Si-SiGe n-channel MOSFET performance of single-and dual-surface channel devices fabricated using 15% Ge content SiGe virtual substrates are presented. Device fabrication used high thermal budget processes and virtual substrates were not polished. Mobility enhancement factors exceeding 1.6 are demonstrated for both single-and dual-channel device architectures compared with bulk-Si control devices. Single-channel devices exhibit improved gate oxide quality, and larger mobility enhancements, at higher vertical effective fields compared with the dual-channel strain-compensated devices. The compromised performance enhancements of the dual-channel devices are attributed to greater interface roughness and increased Ge diffusion resulting from the Si/sub 0.7/Ge/sub 0.3/ buried channel layer.
39 citations
"Study of substrate induced strained..." refers background in this paper
...This property has already been exploited to demonstrate high-speed devices compared to conventional-Si MOSFETs [2-4]....
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