Study of the quasi-saturation effect in VDMOS transistors
TL;DR: In this article, the quasi-saturation effect in VDMOS transistors is studied in detail, and it is shown that such behavior is due to carrier velocity saturation in the JFET region of the device.
Abstract: The quasi-saturation effect in VDMOS transistors is studied in detail. It is shown that such behavior is due to carrier velocity saturation in the JFET region of the device. Two-dimensional numerical simulation is carried out to study the quasi-saturation effect and its relation to different device design parameters. Experimental results over a wide range of voltage and current levels are used to verify calculated dc characteristics. In addition, the design constraint on p-body spacing in order to avoid the quasi-saturation effect is defined.
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TL;DR: In this paper, the authors discuss some limitations in the approaches commonly adopted for device and circuit electro-thermal simulation and propose a new approach for calculating the temperature distribution under both steady-state and transient conditions.
Abstract: This paper discusses some limitations in the approaches commonly adopted for device and circuit electro-thermal simulation Thermal models for circuit simulation assume a simple geometry for the region where power dissipation occurs Available models are compared The impact of model parameters and bias condition on simulation accuracy is discussed A new approach for calculating the temperature distribution under both steady-state and transient conditions is also proposed The accuracy of two-dimensional (2D) electro-thermal device simulations is then investigated It is shown that 2D simulations can lead to markedly inaccurate results Possible approaches to overcome these limitations are discussed
82 citations
TL;DR: In this article, the surface potential-based compact transistor model, MOS Model 20 (MM20), has been extended with a quasi-saturation, an effect that is typical for LDMOS devices with a long drift region.
Abstract: The surface-potential-based compact transistor model, MOS Model 20 (MM20), has been extended with a quasi-saturation, an effect that is typical for LDMOS devices with a long drift region. As a result, MM20 extends its application range from low-voltage LDMOS devices up to high-voltage LDMOS devices of about 100V. In this paper, the new dc model of MM20, including quasi-saturation, is presented. The addition of velocity saturation in the drift region ensures the current to be controlled by either the channel region or the drift region. A comparison with dc measurements on a 60-V LDMOS device shows that the new model provides an accurate description in all regimes of operation, ranging from subthreshold to superthreshold, in both the linear and saturation regime. Thus, owing to the inclusion of quasi-saturation also the regime of high-gate and high-drain bias conditions for high-voltage LDMOS devices is accurately described.
76 citations
Cites background from "Study of the quasi-saturation effec..."
...For high-voltage LDMOS devices (which consequently have a long drift region), however, velocity saturation can occur in the drift region of the device [2], an operating regime generally referred to as quasi-saturation....
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11 Jun 1990
TL;DR: In this paper, a novel methodology for modeling power MOS devices using a SPICE-compatible subcircuit is proposed, where the interelectrode capacitances are modeled accurately as nonlinear functions of the applied biases.
Abstract: A novel methodology for modeling power MOS devices using a SPICE-compatible subcircuit is proposed. The interelectrode capacitances are modeled accurately as nonlinear functions of the applied biases. Simulations and measured data support the accuracy of the new models. Various second-order effects relating to the gate capacitance model are discussed, and stratagies are presented to include them in the model. The model parameters can be obtained from device measurements. The approach is verified by gate charge measurements over a wide range of applied biases. >
74 citations
Cites background from "Study of the quasi-saturation effec..."
...Others have described the quasi-saturation effect in high voltage MOS devices [ 8 ]....
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01 Jan 2006
TL;DR: In this paper, the surface potential-based compact transistor model, MOS Model 20 (MM20), has been extended with a quasi-saturation, an effect that is typical for LDMOS devices with a long drift region.
Abstract: The surface-potential-based compact transistor model, MOS Model 20 (MM20), has been extended with a quasi-saturation, an effect that is typical for LDMOS devices with a long drift region As a result, MM20 extends its application range from low-voltage LDMOS devices up to high-voltage LDMOS devices of about 100V In this paper, the new dc model of MM20, including quasi-saturation, is presented The addition of velocity saturation in the drift region ensures the current to be controlled by either the channel region or the drift region A comparison with dc measurements on a 60-V LDMOS device shows that the new model provides an accurate description in all regimes of operation, ranging from subthreshold to superthreshold, in both the linear and saturation regime Thus, owing to the inclusion of quasi-saturation also the regime of high-gate and high-drain bias conditions for high-voltage LDMOS devices is accurately described
70 citations
TL;DR: In this paper, a charge-based model for vertical DMOSTs is developed and implemented in SPICE, which is derived from regional quasi-static analyses of carrier transport which implicitly characterize the device currents and charges and which require numerical solution Newton-Raphson iterative device solutions.
Abstract: A physical, seminumerical charge-based model for vertical DMOSTs is developed and implemented in SPICE The model is derived from regional quasi-static analyses of carrier transport which implicitly characterize the device currents and charges and which require numerical solution Newton-Raphson iterative device solutions are derived within the circuit nodal analysis framework of SPICE PISCES simulations and measurements of test devices support the model, which is demonstrated in DC and transient SPICE simulations of VDMOSTs and high-voltage integrated circuits (HVICs) >
66 citations
References
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01 Nov 1952
TL;DR: In this article, the authors proposed a new form of transistor called unipolar field effect transistor, which is of the "field effect" type in which the conductivity of a layer of semiconductor is modulated by a transverse electric field.
Abstract: The theory for a new form of transistor is presented. This transistor is of the "field-effect" type in which the conductivity of a layer of semiconductor is modulated by a transverse electric field. Since the amplifying action involves currents carried pre-dominantly by one kind of carrier, the name "unipolar" is proposed to distinguish these transistors from point-contact and junction types, which are "bipolar" in this sense. Regarded as an analog for a vacuum-tube triode, the unipolar field-effect transistor may have a m? of 10 or more, high output resistance, and a frequency response higher than bipolar transistors of comparable dimensions.
645 citations
TL;DR: In this paper, the field dependence of mobility has been determined for electrons and holes in both germanium and silicon, and the observed critical field at 298\ifmmode^\circ\else\textdegree\fi{}K beyond which $\ensuremath{\mu}$ varies as ${E}^{-}\frac{1}{2}}$.
Abstract: The field dependence of mobility has been determined for electrons and holes in both germanium and silicon. The observed critical field at 298\ifmmode^\circ\else\textdegree\fi{}K beyond which $\ensuremath{\mu}$ varies as ${E}^{\ensuremath{-}\frac{1}{2}}$ is 900 volts/cm for $n$-type germanium, 1400 volts/cm for $p$-type germanium, 2500 volts/cm for $n$-type silicon, and 7500 volts/cm for $p$-type silicon. These values of critical field are between two to four times those calculated on the basis of spherical constant energy surfaces in the Brillouin zone. A saturation drift velocity of ${6(10)}^{6}$ cm/sec is observed in germanium which is in good agreement with predictions based on scattering by the optical modes. Data on $n$-type germanium at 20\ifmmode^\circ\else\textdegree\fi{}K show a range over which impurity scattering decreases and the mobility increases with field until lattice scattering dominates as at the higher temperatures.
292 citations
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TL;DR: This paper reviews the progress in device modeling with emphasis on numerical modeling approaches and describes different numerical models, mainly developed in the past decade, and discretization as well as solution methods are being discussed.
Abstract: This paper reviews the progress in device modeling with emphasis on numerical modeling approaches. The reason for this is its ever-increasing importance for the design of small-scale devices suited for VLSI applications. First, the basic field equations with their respective boundary conditions are given. Followed by a description of empirical models for the physical device mechanisms, i.e., mobility, avalanche generation, band-gap narrowing. Subsequently, different numerical models, mainly developed in the past decade, are outlined briefly and discretization as well as solution methods are being discussed. Some remarks are given concerning the relations between finite-difference and finite-element methods. Simplified numerical models are also mentioned and their usefulness for certain type of applications is stressed. In order to clearly demonstrate the power of numerical device modeling, a number of representative examples is given. The last sections deal with analytical device modeling. Bipolar transistor models are only briefly reviewed since the evolution has led to some kind of standardization, but the development of MOS transistor models, where the same is not true, is described in more detail. Cross references to numerical results should clarify that with decreasing device dimensions the model parameters of analytical MOST models tend to loose their physical significance and change increasingly into fitting parameters.
124 citations
TL;DR: In this paper, the authors present a model for the on-state resistance of power vertical, double-diffused MOS transistors with emphasis on cell layout optimization and supporting experimental data.
Abstract: We present a model for the on-state resistance of power vertical, double-diffused MOS (VDMOS) transistors with emphasis on cell layout optimization and supporting experimental data. Essentially the same minimum R on can be achieved using any of six different cellular cell geometries including square and hexagonal cells. Specifically, the on-resistances of all cellular designs are essentially identical if they have the same p-well width and the same ratio of well area to cell area. Cellular designs yield lower on-resistance than linear-cell designs unless the latter, through clever layout perhaps, allows at least 1.6 times smaller well width than the former. Design examples and experiments illustrate a simple optimization procedure, which starts with choosing the minimum p-well width and depth compatible with production technology and then finding the optimum spacing between the p-wells.
96 citations