Journal ArticleDOI
Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique
Junil Lee,Ryoongbin Lee,Sihyun Kim,Kitae Lee,Hyun-Min Kim,So Youn Kim,Munhyeon Kim,Sangwan Kim,Jong-Ho Lee,Byung-Gook Park +9 more
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TLDR
In this paper, a tunnel field effect transistor (TFET) with surface Ge-rich SiGe nanowire as a channel has been demonstrated, and the TFET with the concentration-graded SiGe channel can improve drive current due to a smaller band gap at the Gecondensed surface of the channel compared to Si or non-condensed SiGe channels TFET.Abstract:
In this study, tunnel field-effect transistor (TFET) which has surface Ge-rich SiGe nanowire as a channel has been demonstrated. There are improvements in terms of on-current and subthreshold swing (SS) comparing with control groups (constant Ge concentration SiGe TFET and Si TFET) fabricated by the same process flow except for the channel formation step. In order to obtain the concentration-graded SiGe channel, Ge condensation method which is a kind of oxidation is adopted. The rectangular shape of the channel becomes a rounded nanowire through the Ge condensation process. The TFET with the concentration-graded SiGe channel can improve drive current due to a smaller band gap at the Ge-condensed surface of the channel compared to Si or non-condensed SiGe channel TFET.read more
Citations
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Journal ArticleDOI
Drain Dielectric Pocket Engineering: its Impact on the Electrical Performance of a Hetero-Structure Tunnel FET
Shwetapadma Panda,S. Dash +1 more
Journal ArticleDOI
p-Channel TFET Operation of Bilayer Structures With Type-II Heterotunneling Junction of Oxide- and Group-IV Semiconductors
Kimihiko Kato,Kwang-Won Jo,Hiroaki Matsui,Hitoshi Tabata,Takahiro Mori,Yukinori Morita,Takashi Matsukawa,Mitsuru Takenaka,Shinichi Takagi +8 more
TL;DR: In this article, a p-channel bilayer TFET composed of an n-type oxide semiconductor (n-OS)/p-type group-IV semiconductor heterostructure was proposed.
Journal ArticleDOI
Analysis of Current Variation with Work Function Variation in L-Shaped Tunnel-Field Effect Transistor
TL;DR: The band-to-band tunneling (BTBT) rate according to WFV cases shows that when ION is formed in L-shaped TFET, the BTBT rate relies on theWFV in the whole region of the gate because the tunnel barrier isformed in the entire area where the source and the gate meet.
Journal ArticleDOI
Optimal Design and Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor
Journal ArticleDOI
Source engineering for bilayer tunnel field effect transistor with hetero tunnel junction: Thickness and impurity concentration
Kimihiko Kato,Takahiro Mori,Yukinori Morita,Takashi Matsukawa,Mitsuru Takenaka,Shinichi Takagi +5 more
TL;DR: In this paper, the authors investigated the impacts of a source layer thickness, a source impurity concentration and a channel thickness in a bilayer TFET with a thin-film hetero tunneling junction on the electrical characteristics.
References
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Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Journal ArticleDOI
The si-sio, interface – electrical properties as determined by the metal-insulator-silicon conductance technique
E. H. Nicollian,A. Goetzberger +1 more
TL;DR: In this article, a realistic characterization of the Si-SiO 2 interface is developed, where a continuum of states is found across the band gap of the silicon, and the dominant contribution in the samples measured arises from a random distribution of surface charge.
Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
MOS capacitance measurements for high-leakage thin dielectrics
K.J. Yang,Chenming Hu +1 more
TL;DR: In this article, a new technique is presented which allows the frequency-independent device capacitance to be accurately extracted from impedance measurements at two frequencies for a 1.7 nm SiO/sub 2/ capacitor.
Journal ArticleDOI
CMOS Scaling Trends and Beyond
Mark T. Bohr,Ian A. Young +1 more
TL;DR: Trends in CMOS scaling over the past decade are described and some of the new device options and technology directions being explored to continue scaling into the future are discussed.