Survey of low power testing of VLSI circuits
01 Mar 2012-pp 1-7
TL;DR: Low power dissipation during test application is becoming increasingly important in today's V LSI systems design and is a major goal in the future development of VLSI design.
Abstract: The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, reduced autonomy of portable systems, and decrease of overall yield. Low power dissipation during test application is becoming increasingly important in today's VLSI systems design and is a major goal in the future development of VLSI design.
Citations
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TL;DR: This paper proposes a novel test pattern generator (TPG) for built-in self-test that generates multiple single-input change vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector.
Abstract: This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our method generates multiple single-input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed TPG is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results show that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. The performances of the designed TPGs and the circuits under test with 45 nm are evaluated. Simulation results with ISCAS benchmarks demonstrate that MSIC can save test power and impose no more than 7.5% overhead for a scan design. It also achieves the target fault coverage without increasing the test length.
35 citations
Cites background from "Survey of low power testing of VLSI..."
...They can also damage the circuit and reduce product yield and lifetime [2], [3]....
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22 Mar 2010
TL;DR: It is demonstrated that the performance binning overhead of a 64-core processor can be decreased by 51% and 36% using the proposed variation-aware core clustering and curve fitting strategies respectively.
Abstract: Number of cores per multi-core processor die, as well as variation between the maximum operating frequency of individual cores, is rapidly increasing. This makes performance binning of multi-core processors a non-trivial task. In this paper, we study, for the first time, multi-core binning metrics and strategies to evaluate them efficiently. We discuss two multi-core binning metrics with high correlation to processor throughput for different types of workloads and different process variation scenarios. More importantly, we demonstrate the importance of leveraging variation model data in the binning process to significantly reduce the binning overhead with a negligible loss in binning quality. For example, we demonstrate that the performance binning overhead of a 64-core processor can be decreased by 51% and 36% using the proposed variation-aware core clustering and curve fitting strategies respectively. Experiments were performed using a manufacturing variation model based on real 65nm silicon data.
34 citations
TL;DR: Experimental results show that the proposed novel X-filling technique, namely “iFill”, can guarantee the power safety in both shift and capture phases during at-speed scan-based testing.
Abstract: Power consumption during at-speed scan-based testing can be significantly higher than that during normal functional mode in both shift and capture phases, which can cause circuits' reliability concerns during manufacturing test. This paper proposes a novel X-filling technique, namely “iFill”, to address the above issue, by analyzing the impact of X-bits on switching activities of the circuit nodes in the two different phases. In addition, different from prior X -filling methods for shift-power reduction that can only reduce shift-in power, our method is able to cut down power consumptions in both shift-in and shift-out processes. Experimental results on benchmark circuits show that the proposed technique can guarantee the power safety in both shift and capture phases during at-speed scan-based testing.
30 citations
Dissertation•
14 Nov 2014
TL;DR: In this article, the synthese de mes travaux de recherche and denseignement effectues depuis septembre 1998, date a laquelle j’ai debute ma these de doctorat.
Abstract: Ce document presente la synthese de mes travaux de recherche et d’enseignement effectues depuis septembre 1998, date a laquelle j’ai debute ma these de doctorat. Les travaux de recherche ont ete effectues au LIRMM (Laboratoire d’Informatique, de Robotique et de Microelectronique de Montpellier) au sein du departement de Microelectronique. Les activites d’enseignement ont ete menees a la Faculte des sciences (ex UFR) / departement EEA (Electronique, Electrotechnique et Automatique) de l’Universite Montpellier 2 au niveau Licence et Master.
29 citations
References
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06 Apr 1993
TL;DR: A BIST scheduling process that takes into consideration constraints is presented, and a new BIST control methodology is introduced, that implements the BIST schedule with a highly modular architecture.
Abstract: BIST is a viable approach to test today's digital systems. Constraints, such as power, noise, area overhead, and others, limit the possibilities of parallel BIST execution in complex VLSI devices. This paper presents a BIST scheduling process that takes into consideration such constraints, and introduces a new BIST control methodology, that implements the BIST schedule with a highly modular architecture. In fact, due to the uniformity of interface, the BIST control elements are independent of the BIST scheme used in the embedded blocks of a device. This BIST control architecture can provide block level diagnostic information. >
551 citations
"Survey of low power testing of VLSI..." refers background in this paper
...VLSI circuit designers are excited by the prospect of addressing these challenges efficiently, but these challenges are becoming increasingly hard to overcome[1-3]...
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...To provide an adequate response to these industrial needs, various researchers have proposed solutions for power problems encountered during test.[1-3]...
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Book•
01 Jul 2006
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
522 citations
"Survey of low power testing of VLSI..." refers methods in this paper
...The low power test data compression techniques can be divided into three main categories [22]: coding-based techniques, linear-decompression-based techniques (LFSR reseeding techniques) and broadcast-scan-based technique....
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Book•
21 Jul 2006
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Abstract: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
· Most up-to-date coverage of design for testability.
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.
Table of Contents
Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation
Chapter 4 - Test Generation
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age
340 citations
TL;DR: Heuristics with good performance bounds can be derived for combinational circuits tested using built-in self-test (BIST) and considerable reduction in power dissipation can be obtained using the proposed techniques.
Abstract: Reduction of power dissipation during test application is studied for scan designs and for combinational circuits tested using built-in self-test (BIST). The problems are shown to be intractable. Heuristics to solve these problems are discussed. We show that heuristics with good performance bounds can be derived for combinational circuits tested using BIST. Experimental results show that considerable reduction in power dissipation can be obtained using the proposed techniques.
338 citations
03 Oct 2000
TL;DR: A method of adapting conventional scan architectures such that they operate in a low power mode during test so that they maintain the test times of the pre-adapted scan architectures.
Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. This paper describes a method of adapting conventional scan architectures such that they operate in a low power mode during test. The adapted scan architectures maintain the test times of the pre-adapted scan architectures. Also, the adaptation occurs in a manner that enables the test patterns of the pre-adapted scan architecture to be directly reusable in the adapted scan architecture.
305 citations
"Survey of low power testing of VLSI..." refers background in this paper
...In [18] the scan-chain is partitioned into N segments where only one segment is active at a time....
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