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Switched Capacitor Filters: Theory, Analysis and Design

TL;DR: In this article, the authors present a detailed analysis of the Switched-Capacitor Ladder Filters based on Impedence Simulation and on Multiloop Feedback Concepts.
Abstract: MOS Technology and Sampled Data Filters. Analysis of Switched-Capacitor Networks. Passive Switched-Capacitor Networks. First-Order Active Switched-Capacitor Networks. Second-Order Active SC Filters. Switched-Capacitor Ladder Filters Based on Impedence Simulation. SC Filters Based on Operational Simulation of LC Ladders and on Multiloop Feedback Concepts. Switched-Capacitor N-Path Filters. Practical Considerations in the Design of Switched-Capacitor Networks and Their Applications. Appendices.
Citations
More filters
Journal ArticleDOI
TL;DR: A design methodology for synthesis of active N-path bandpass filters is introduced and a 0.1-to-1.2 GHz tunable 6th-order N- path channel-select filter in 65 nm LP CMOS is introduced, achieving a “flat” passband shape and high out-of-band linearity.
Abstract: A design methodology for synthesis of active N-path bandpass filters is introduced. Based on this methodology, a 0.1-to-1.2 GHz tunable 6th-order N-path channel-select filter in 65 nm LP CMOS is introduced. It is based on coupling N-path filters with gyrators, achieving a “flat” passband shape and high out-of-band linearity. A Miller compensation method is utilized to considerably improve the passband shape of the filter. The filter has 2.8 dB NF, +25 dB gain, +26 dBm wideband IIP3 ( MHz), an out-of-band 1 dB blocker compression point B1dB,CP of +7 dBm (Δf = +50 MHz) and 59 dB stopband rejection. The analog and digital part of the filter draw 11.7 mA and 3-36 mA from 1.2 V, respectively. The LO leakage to the input port of the filter is ≤-64 dBm at a clock frequency of 1 GHz. The proposed filter only consists of inverters, switches and capacitors and therefore it is friendly with process scaling.

156 citations


Cites background from "Switched Capacitor Filters: Theory,..."

  • ...On the other hand, N-path filters [13]–[23] can provide us with: 1) a flexibly tunable center frequency and 2) potentially high -factor and DR....

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Journal ArticleDOI
TL;DR: A widely tunable 4th order BPF based on the subtraction of two 2nd order 4-path passive-mixer filters with slightly different center frequencies is proposed.
Abstract: A widely tunable 4th order BPF based on the subtraction of two 2nd order 4-path passive-mixer filters with slightly different center frequencies is proposed. The center frequency of each 4-path filter is slightly shifted relative to its clock frequency (one upward and the other one downward) by agm-C technique. Capacitive splitting of the input signal is used to reduce the mutual loading of the two 4-path BPFs and increase their quality factors. The filter is tunable from 0.4 GHz to 1.2 GHz with approximately constant bandwidth of 21 MHz. The in-band 1-dB compression point of the filter is -4.4 dBm while the in-band IIP3 of the filter is +9 dBm and the out-of-band IIP3 is + 29 dBm (Δf=+50 MHz). The ultimate rejection of the filter is >; 55 dB and the NF of the filter is 10 dB. The static and dynamic current consumption of the filter are 2.8 mA from 2.5 V and 12 mA from 1.2 V, respectively (at 1 GHz). The LO leakage power to the input port is <; - 60 dBm. The filter has been fabricated in CMOS LP 65 nm technology and the active area is 0.127 mm2.

131 citations

Journal ArticleDOI
TL;DR: This work analyzes several examples of switched linear circuits and a switched spring-mass system to illustrate the physical manifestations of regressivity and nonregressivity for discrete and continuous time systems as well as hybrid discrete/continuous systems from a time scales perspective.

53 citations

Journal ArticleDOI
TL;DR: Switched-capacitor fractional-step filter design of low-pass filter prototypes with Butterworth characteristics is reported for the first time using discrete-time integrators which implement both the bilinear and the Al-Alaoui s-to-z transformations.
Abstract: Switched-capacitor fractional-step filter design of low-pass filter prototypes with Butterworth characteristics is reported in this work for the first time. This is achieved using discrete-time integrators which implement both the bilinear and the Al-Alaoui s-to-z transformations. Filters of orders 1.2, 1.5 and 1.8 as well as 3.2, 3.5, and 3.8 are designed and verified using transistor-level simulations with Cadence on AMS $$0.35\,\upmu $$0.35μm CMOS process. Digital programmability of the fractional-step filters is also achieved.

39 citations


Cites background or methods from "Switched Capacitor Filters: Theory,..."

  • ...The realization of the filter transfer function (4) can be performed using the inverse follow-the-leader feedback (IFLF) topology [14] which has a transfer function given by...

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  • ...An attractive and precise technique for realizing voltage-mode resistorless filters is known to be the switchedcapacitor (SC) technique, where the realized time-constants are formed as a product of a clock period and the ratio of the associated capacitors [5,14]....

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Journal ArticleDOI
TL;DR: In this article, a novel field-programmable analog array (FPAA) architecture based on switched-capacitor techniques is proposed, where each configurable analog block (CAB) in the proposed architecture is an opamp with feedback switches which are controlled by configuration bits.
Abstract: A novel field-programmable analog array (FPAA) architecture based on switched-capacitor techniques is proposed. Each configurable analog block (CAB) in the proposed architecture is an opamp with feedback switches which are controlled by configuration bits. Interconnection networks are used to connect programmable capacitor arrays (PCAs) and the CABs. The routing switches in the interconnection networks not only function as interconnection elements but also switches for the charge transfer required in switched-capacitor circuits. This scheme minimizes the number of connecting switches between CABs and PCAs, thereby, it reduces the settling time of the resultant SC circuits and thus achieving high speed operation. The architecture is highly flexible and provides for the implementation of various A/D and D/A converters when the FPAA is connected with external digital circuits or field-programmable gate arrays (FPGAs).

34 citations