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Journal Article•DOI•

Switched-capacitor multiply-by-two amplifier with reduced capacitor mismatches sensitivity and full swing sample signal common-mode voltage

01 Nov 2012-Journal of Semiconductors (IOP Publishing)-Vol. 33, Iss: 11, pp 115003
TL;DR: In this article, a switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed, which is based on associating two sets of two capacitors in cross series during the amplification phase.
Abstract: A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed. This structure is based on associating two sets of two capacitors in cross series during the amplification phase. This circuit permits the common-mode voltage of the sample signal to reach full swing. Using the charge-complement technique, the proposed amplifier can reduce the impact of parasitic capacitors on the gain accuracy effectively. Simulation results show that as sample signal common-mode voltage changes, the difference between the minimum and maximum gain error is less than 0.03%. When the capacitor mismatch is increased from 0 to 0.2%, the gain error is deteriorated by 0.00015%. In all simulations, the gain of amplifier is 69 dB.
Citations
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Proceedings Article•DOI•
26 Jul 2019
TL;DR: In this paper, a multiply-by-n switched capacitor amplifier, for n greater than 2, whose gain is insensitive to capacitance mismatch is presented, and the simulation results show that the variation in gain due to capacitor mismatch is much lesser than conventional architectures.
Abstract: Precision multiply-by-2 amplifiers have been researched intensively due to their use in pipelined analog-to-digital converters. For integer gains greater than 2, not much work has been reported. This work presents a multiply-by-n switched capacitor amplifier, for n greater than 2, whose gain is insensitive to capacitor mismatch. Simulation results show that the variation in gain due to capacitance mismatch is much lesser than conventional architectures.

Cites background or methods from "Switched-capacitor multiply-by-two ..."

  • ...[6] used two sets of two capacitors in cross series, and the charge complement technique, to reduce mismatch errors, and also to enable a full common-mode input swing....

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  • ...The precision of SC amplifiers depends primarily on capacitance mismatches [1-7], nonidealities of the MOS switch [8-12], and nonidealities in the operational amplifier....

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References
More filters
Book•
01 Jan 1996
TL;DR: In this paper, the authors present an overview of current mirror and Opamp design and compensation for single-stage Amplifiers and Current Mirrors, as well as a comparison of the two types of Opamps.
Abstract: Partial table of contents: Integrated--Circuit Devices and Modelling. Processing and Layout. Basic Current Mirrors and Single--Stage Amplifiers. Noise Analysis and Modelling. Basic Opamp Design and Compensation. Advanced Current Mirrors and Opamps. Comparators. Switched--Capacitor Circuits. Nyquist--Rate D/A Converters. Oversampling Converters. Phase--Locked Loops. Index.

3,118 citations


Additional excerpts

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Book•
31 Oct 2002
TL;DR: In this article, the authors present a number of low voltage low-voltage techniques, including double sampling with a MOS Transistor Switch, clock generation, and switched opAmp technique.
Abstract: 1. Introduction. 2. Low Voltage Issues. 3. Sample-and-Hold Operation. 4. A/D Converters. 5. S/H Circuit Architectures. 6. Sampling with a MOS Transistor Switch. 7. Operational Amplifiers. 8. Clock Generation. 9. Double-Sampling. 10. Switched OpAmp Technique. 11. Other Low-Voltage Techniques. 12. Prototypes and Experimental Results. 13. Conclusions. Appendices: Derivation of OTA GBW Requirement. Optimum Input Capacitance. Saturation Voltage.

93 citations

Journal Article•DOI•
07 Feb 2000
TL;DR: Capacitor error-averaging offers an advantage of achieving both INL and DNL improvements over that achievable by capacitor matching, but it requires three clock phases-one extra clock phase for averaging capacitor errors.
Abstract: The performance of high-resolution pipelined ADCs is limited by the residue amplifier gain and settling accuracy. In typical implementations, error sources are capacitor ratio mismatch, op-amp gain, and residue settling. All these affect ADC performance adversely, specifically in high-speed ADCs. Capacitor matching improves as capacitor size increases, but the trend is towards shrinking capacitor size for high-speed conversion. Many innovations to overcome this such as ratio-independent techniques are reported. Among them, capacitor error-averaging offers an advantage of achieving both INL and DNL improvements over that achievable by capacitor matching, but it requires three clock phases-one extra clock phase for averaging capacitor errors. In this work, the one extra clock phase is used advantageously for comparison.

75 citations

Journal Article•DOI•
TL;DR: A wide-dynamic-range CMOS image sensor based on synthesis of one long and multiple short exposure-time signals is proposed, and a high-speed, high-resolution column-parallel integration type analog-to-digital converter with a nonlinear slope is crucial for this purpose.
Abstract: A wide-dynamic-range CMOS image sensor based on synthesis of one long and multiple short exposure-time signals is proposed. A high-speed, high-resolution column-parallel integration type analog-to-digital converter (ADC) with a nonlinear slope is crucial for this purpose. A prototype wide-dynamic-range CMOS image sensor that captures one long and three short exposure-time signals has been developed using 0.25-mum 1-poly 4-metal CMOS image sensor technology. The dynamic range of the prototype sensor is expanded by a factor of 121.5, compared with the case of a single long exposure time. The maximum DNL of the ADC is 0.3 least significant bits (LSB) for the single-resolution mode and 0.7 LSB for the multiresolution mode

64 citations

Proceedings Article•DOI•
P. Quinn1, M. Pribytko1•
03 Dec 2003
TL;DR: A floating buffer is proposed which enables the accurate addition of signal voltages without requiring precision components in the basic 1.5-bit ADC stage common to switched capacitor algorithmic and pipelined ADCs.
Abstract: This paper presents a novel circuit architecture for the accurate realization of the basic 1.5-bit ADC stage common to switched capacitor algorithmic and pipelined ADCs. A floating buffer is proposed which enables the accurate addition of signal voltages without requiring precision components. 14-bit ADC linearity is demonstrated with uncharacterized metal-metal capacitors without the need for calibration or trimming. A prototype 12-bit 3.3 MS/s algorithmic ADC in 0.25 /spl mu/m standard CMOS is described. The power FOM is 1.2 pJ/conversion and the area FOM is 31 nm/sup 2//conversion - well below previously reported figures for algorithmic ADCs.

26 citations