Synthesis of a control unit from instruction set specification in VHDL environment
04 Jan 1991-pp 200-205
TL;DR: A methodology for specifying an instruction set in VHDL is proposed and a system for synthesizing controller for the target processor is presented, to serve as a tool in early evaluation of instruction sets for implementation in a processor design environment.
Abstract: Automated design of control structures for digital systems has been one of the active areas of research in high level synthesis. This paper proposes a methodology for specifying an instruction set in VHDL and also presents a system for synthesizing controller for the target processor. The goal of this system is to serve as a tool to help in early evaluation of instruction sets for implementation in a processor design environment. The system accepts the instruction set specification and a microarchitecture description and generates a finite state machine controller. A suitable subset of VHDL has been defined for easy specification of instruction set. Facilities have also been provided to define system timings and to specify clock synchronous activities of the processor. The output is given in VTI FSM compiler format for further processing to generate PLA or standard cell implementation of the controller. >
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11 Nov 1989
TL;DR: A comprehensive terminology for the area is presented, as well as a general model of processor behavior suitable for comparing the algorithms, and the conceptual distinction between data dependency and conflict analysis is emphasized.
Abstract: Microcode compaction is an essential tool for the compilation of high-level language microprograms into microinstructions with parallel microoperations. Although guaranteeing minimum execution time is an exponentially complex problem, recent research indicates that it is not difficult to obtain practical results. This paper, which assumes no prior knowledge of microprogramming on the part of the reader, surveys the approaches that have been developed for compacting microcode. A comprehensive terminology for the area is presented, as well as a general model of processor behavior suitable for comparing the algorithms. Execution examples and a discussion of strengths and weaknesses are given for each of the four classes of loc .al compaction algorithms: linear, critical path, branch and bound, and list scheduling. Local compaction, which applies to jump-free code, is fundamental to any compaction technique. The presentation emphasizes the conceptual distinction between data dependency and conflict analysis.
218 citations
TL;DR: A survey of microcode compaction algorithms can be found in this paper, where a general model of processor behavior suitable for comparing the algorithms is presented. But the authors emphasize the conceptual distinction between data dependency and conflict analysis.
Abstract: Microcode compaction is an essential tool for the compilation of high-level language microprograms into microinstructions with parallel microoperations. Although guaranteeing minimum execution time is an exponentially complex problem, recent research indicates that it is not difficult to obtain practical results. This paper, which assumes no prior knowledge of microprogramming on the part of the reader, surveys the approaches that have been developed for compacting microcode. A comprehensive terminology for the area is presented, as well as a general model of processor behavior suitable for comparing the algorithms. Execution examples and a discussion of strengths and weaknesses are given for each of the four classes of loc .al compaction algorithms: linear, critical path, branch and bound, and list scheduling. Local compaction, which applies to jump-free code, is fundamental to any compaction technique. The presentation emphasizes the conceptual distinction between data dependency and conflict analysis.
209 citations
TL;DR: The authors discuss in detail the synthesis of structures from behavioural domain descriptions using a formal language, internal representation of the behaviour, synthesis based on data-flow analysis, optimizations and generation of a hardware structure.
Abstract: The authors discuss in detail the synthesis of structures from behavioural domain descriptions. The overall synthesis approach is explained, the techniques and methods used to solve the main problems are discussed, implementation results are given, and experiences with various examples are described. The principal topics that are addressed are design description in the behavioural domain using a formal language, internal representation of the behaviour, synthesis based on data-flow analysis, optimizations and generation of a hardware structure. These techniques were implemented in the Karlsruhe DSL synthesis system. >
156 citations
02 Jul 1986
TL;DR: Methodologies based on simple components, such as gate arrays and standard cells, are not adequate when designing complex VLSI systems.
Abstract: Methodologies based on simple components, such as gate arrays and standard cells, are not adequate when designing complex VLSI systems. Silicon compilation, an evolutionary step from standard cell methodology, offers an increase in design complexity with an increase in design productivity. Silicon compilers can be broadly divided into structural, functional, and intelligent silicon compilers ([GajsSS]). In structural silicon compilation, the designer explicitly defines the microarchitecture; i.e. a structure consisting of registers, busses, RAMS and ALUs. Functional silicon compilers transform a behavioral description into a microarchitecture automatically.
59 citations
01 Jun 1989
TL;DR: A structured modeling methodology is presented which suggests standard practices for writing VHDL descriptions which span a variety of design models and produces a structural description of generic components.
Abstract: This paper describes the use of VHDL in a behavioral synthesis system. A structured modeling methodology is presented which suggests standard practices for writing VHDL descriptions which span a variety of design models. The VHDL Synthesis System (VSS) processes each of these input descriptions and produces a structural description of generic components.
28 citations