Patent•
System and method for platform sleep state enhancements using non-volatile dual in-line memory modules
30 May 2019-
TL;DR: In this paper, a system and method for performing sleep state enhancements in a computing device using firmware and NVDIMMs that include DRAM and flash memory is discussed, where flash-backed DRAM covers all of platform memory.
Abstract: A system and method for performing sleep state enhancements in a computing device using firmware and NVDIMMs that include DRAM and flash memory is discussed. The flash-backed DRAM covers all of platform memory. All writes to DRAM during system operation are propagated to the flash. Sleep state requests trigger a System Management Interrupt and a firmware a SMI handler handles the sleep state request so as to enable power savings during the sleep state and facilitate faster resume times when exiting the sleep state.
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Patent•
07 Feb 2019TL;DR: In this article, the authors present an embodiment of a semiconductor package apparatus that includes technology to determine if a wake event corresponds to a zero-power state of a computer operating system.
Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if a wake event corresponds to a zero-power state of a computer operating system, determine if a run-time state is valid to wake the operating system from the zero-power state, and wake the operating system from the zero-power state to the run-time state if the run-time state is determined to be valid. Other embodiments are disclosed and claimed.
1 citations
References
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Patent•
11 Feb 2009
TL;DR: A memory device for use with a primary power source includes: volatile memory including a plurality of memory portions each of which has a normal operating state and a low-power state; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary source as discussed by the authors.
Abstract: A memory device for use with a primary power source includes: volatile memory including a plurality of memory portions each of which has a normal operating state and a low-power state; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source; a non-volatile memory; and a controller in communication with the volatile memory and the non-volatile memory programmed to detect a loss of power of the primary power source and in response to move data from the volatile memory to the non-volatile memory at least one memory portion at a time, and while moving data from the volatile memory to the non-volatile memory place the memory portions from which data is being moved into a normal operating state and the memory portions from which data is not being moved into a low-power state.
81 citations
Patent•
09 Sep 2016
TL;DR: In this paper, a graceful shutdown of a computer system is initiated by sending a command to an asynchronous dynamic random access memory refresh (ADR) trigger device to assert an ADR trigger.
Abstract: A graceful shutdown of a computer system is initiated by sending a command to an asynchronous dynamic random access memory refresh (ADR) trigger device to assert an ADR trigger. Responsive to the command, the ADR trigger device asserts the ADR trigger to initiate an ADR of a non-volatile dual in-line memory module (NVDIMM) of the computer system. In response to the ADR trigger being asserted by the ADR trigger device, an ADR of the NVDIMM is performed before completing the graceful shutdown of the computer.
15 citations
Patent•
30 Apr 2012
TL;DR: In this article, a hybrid memory module includes volatile memory and non-volatile memory, and a processor coupled to the hybrid memory is used to prevent it from being mapped during a memory initialization routine.
Abstract: A system includes a hybrid memory module. The hybrid memory module includes volatile memory and non-volatile memory. The system further includes a processor coupled to the hybrid memory module. The processor prevents the hybrid memory module from being mapped during a memory initialization routine by misrepresenting a status of the hybrid memory module.
9 citations
Patent•
12 Nov 2020TL;DR: In this article, the authors present techniques for implementing hybrid memory modules with improved inter-memory data transmission paths, which exhibits improved transmission latencies and power consumption when transmitting data between DRAM devices and NVM devices (e.g., flash devices).
Abstract: Disclosed herein are techniques for implementing hybrid memory modules with improved inter-memory data transmission paths. The claimed embodiments address the problem of implementing a hybrid memory module that exhibits improved transmission latencies and power consumption when transmitting data between DRAM devices and NVM devices (e.g., flash devices) during data backup and data restore operations. Some embodiments are directed to approaches for providing a direct data transmission path coupling a non-volatile memory controller and the DRAM devices to transmit data between the DRAM devices and the flash devices. In one or more embodiments, the DRAM devices can be port switched devices, with a first port coupled to the data buffers and a second port coupled to the direct data transmission path. Further, in one or more embodiments, such data buffers can be disabled when transmitting data between the DRAM devices and the flash devices.
7 citations
Patent•
02 Mar 2021
TL;DR: In this article, the processor selectively replaces the first firmware image on the first memory device with the second firmware image, in response to the first image being different from the second image, the processor associates the device type identifying information with device type information for a second memory device.
Abstract: An Information Handling System (IHS) has persistent memory device(s) coupled to a processor. Each memory device includes a first firmware image, version identifying information associated with the first firmware image, and device type identifying information. A firmware interface suite coupled to the processor has a firmware interface that is executed by the processor. The processor responds to identifying a trigger condition for automatic intra-system firmware update of a persistent memory device. The processor accesses the version identifying information and the device type identifying information for a first memory device containing the first firmware image of the persistent memory device(s). The processor associates the device type identifying information with device type information for a second memory device. In response to the first firmware image being different from the second firmware image, the processor selectively replaces the first firmware image on the first memory device with the second firmware image.
5 citations