System-Level Design Methodologies for Networked Multiprocessor Systems-on-Chip
01 Nov 2008-
TL;DR: The aim has been to develop a general sensor network modeling environment and to bridge the abstraction gap between the system-level abstract sensor network model and the implementation-level, cycle-accurate sensor node model, an intermediate-level bridging model based on transaction-level modeling concepts is introduced.
Abstract: models of various processing elements and simulating the whole system to check if the tasks meet their local and/or end-to-end deadlines under precedence and resource constraints. This work has also formed the basis for other system-level modeling-related research activities such as networks-on-chip and reconfigurable computing platforms. Chapter 6 describes a further extension of our earlier work on SystemC-based multiprocessor system-on-chip modeling framework which can provide the wireless sensor network designers a system-level abstraction of the sensor network for system-level design-space exploration to meet the requirements mentioned above. Though our aim has been to develop a general sensor network modeling environment, we have actually been driven by a real-life sensor network application − the Hogthrob project which, as described above, is concerned with the development of a wireless sensor network infrastructure for sow monitoring. In our SystemC-based modeling framework, a sensor network model is designed following the principle of composition. We model a sensor network at two levels: the sensor network level and the sensor node level. At the sensor node level, a sensor node platform model is split into two sections: the software section for functional simultion of the sensor node platform and the hardware section to enable estimation of the energy consumption of the sensor node platform. The software section of the sensor node platform model consists of the application model, comprising a set of task models and the RTOS model, composed of a set of RTOS services. At the sensor network level, a sensor node platform model is embedded in an environment model that models the environmental phenomena to be sensed by the sensor network application. To bridge the abstraction gap between the system-level abstract sensor network model (mentioned above) and the implementation-level, cycle-accurate sensor node model (mentioned later), we have introduced an intermediate-level bridging model based on transaction-level modeling concepts that attempts to connect the top-level and the bottom-level models in a consistent manner. This model is described in Chapter 6. 1.2 An Outline of the Thesis 23 1.2.3 Wireless Sensor Node Design & Test and Cycle-
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TL;DR: In this paper, the authors present algorithms for the automatic synthesis of real-time controllers by finding a winning strategy for certain games defined by the timed-automata of Alur and Dill.
Abstract: This paper presents algorithms for the automatic synthesis of real-time controllers by finding a winning strategy for certain games defined by the timed-automata of Alur and Dill. In such games, the outcome depends on the players' actions as well as on their timing. We believe that these results will pave the way for the application of program synthesis techniques to the construction of real-time embedded systems from their specifications.
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Journal Article•
TL;DR: In this article, the authors present two new tools to model and analyze sensor networks: Avrora, a fast and accurate sensor network simulator, and AEON, a novel tool built on top of Avroraa, to evaluate the energy consumption and to accurately predict the lifetime of sensor networks.
Abstract: ABSTRACT Simulation is the de-facto standard tool for the evaluation of distributed and communication systems like sensor networks. Most simulation efforts focus on protocol- and algorithm-level issues, thus depending on the right choice and configuration of models. However, as such models commonly neglect time dependent issues, many research challenges, like energy consumption and radio channel utilization still remain. In this article we present two new tools to model and analyze sensor networks: Avrora, a fast and accurate sensor network simulator, and AEON, a novel tool built on top of Avrora, to evaluate the energy consumption and to accurately predict the lifetime of sensor networks. Avrora is a highly scalable instruction-level simulator for sensor network programs. It simulates the execution of the program down to the level of individual clock cycles, a time quantum of about 135 ns. By incorporating state of the art simulation techniques, including an efficiently maintained event queue, fast-forward through sleep-time, and parallel simulation, it can simulate entire networks of nodes in real time. AEON's energy model is based on Avrora and makes use of the cycle accurate execution of sensor node applications for precise energy measurements. Due to limited energy resources, power consumption is a crucial characteristic of sensor networks. AEON uses accurate measurements of node current draw and the execution of real code to enable accurate prediction of the actual power consumption of sensor nodes. Consequently, it prevents erroneous assumptions on node and network lifetime. Moreover, our detailed energy model allows to compare different low power and energy aware approaches in terms of energy efficiency. Thus, it enables a highly precise estimation of the overall lifetime of a sensor network.
15 citations
Journal Article•
TL;DR: In this paper, the interactive verification of a simple interrupt-driven real-time scheduler written in the machine code language of the MIPS R3000 RISC processor was carried out using the interactive theorem prover Ergo.
Abstract: This paper describes the interactive verification of a simple interrupt-driven real-time scheduler written in the machine code language of the MIPS R3000 RISC processor. The formal verification was carried out using the interactive theorem prover Ergo.
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01 Jan 1989TL;DR: This chapter discusses Bisimulation and Observation Equivalence as a Modelling Communication, a Programming Language, and its application to Equational laws.
Abstract: Foreword. 1. Modelling Communication. 2. Basic Definitions. 3. Equational laws and Their Application. 4. Strong Bisimulation and Strong Equivalence. 5. Bisimulation and Observation Equivalence. 6. Further Examples. 7. The Theory of Observation Congruence. 8. Defining a Programming Language. 9. Operators and Calculi. 10. Specifications and Logic. 11. Determinancy and Confluence. 12. Sources and Related Work. Bibliography. Index.
8,625 citations
28 Sep 2002
TL;DR: An in-depth study of applying wireless sensor networks to real-world habitat monitoring and an instance of the architecture for monitoring seabird nesting environment and behavior is presented.
Abstract: We provide an in-depth study of applying wireless sensor networks to real-world habitat monitoring. A set of system design requirements are developed that cover the hardware design of the nodes, the design of the sensor network, and the capabilities for remote data access and management. A system architecture is proposed to address these requirements for habitat monitoring in general, and an instance of the architecture for monitoring seabird nesting environment and behavior is presented. The currently deployed network consists of 32 nodes on a small island off the coast of Maine streaming useful live data onto the web. The application-driven design exercise serves to identify important areas of further work in data sampling, communications, network retasking, and health monitoring.
4,623 citations
TL;DR: Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
Abstract: On-chip micronetworks, designed with a layered methodology, will meet the distinctive challenges of providing functionally correct, reliable operation of interacting system-on-chip components. A system on chip (SoC) can provide an integrated solution to challenging design problems in the telecommunications, multimedia, and consumer electronics domains. Much of the progress in these fields hinges on the designers' ability to conceive complex electronic engines under strong time-to-market pressure. Success will require using appropriate design and process technologies, as well as interconnecting existing components reliably in a plug-and-play fashion. Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies. Overall, these designs will be based on both deterministic and stochastic models. Creating complex SoCs requires a modular, component-based approach to both hardware and software design. Despite numerous challenges, the authors believe that developers will solve the problems of designing SoC networks. At the same time, they believe that a layered micronetwork design methodology will likely be the only path to mastering the complexity of future SoC designs.
3,852 citations
TL;DR: In this paper, the control of a class of discrete event processes, i.e., processes that are discrete, asynchronous and possibly non-deterministic, is studied. And the existence problem for a supervisor is reduced to finding the largest controllable language contained in a given legal language, where the control process is described as the generator of a formal language, while the supervisor is constructed from the grammar of a specified target language that incorporates the desired closed-loop system behavior.
Abstract: This paper studies the control of a class of discrete event processes, i.e. processes that are discrete, asynchronous and possibly nondeter-ministic. The controlled process is described as the generator of a formal language, while the controller, or supervisor, is constructed from the grammar of a specified target language that incorporates the desired closed-loop system behavior. The existence problem for a supervisor is reduced to finding the largest controllable language contained in a given legal language. Two examples are provided.
3,432 citations
22 Jun 2001
TL;DR: This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
Abstract: Using on-chip interconnection networks in place of ad-hoc glo-bal wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. The area overhead required to implement an on-chip network is modest, we estimate 6.6%. This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
3,209 citations