Technology-migratable ASIC library design
IBM1
TL;DR: A library strategy has been developed to enable IBM Microelectronics ASIC development to keep pace with rapid technology enhancements and to offer leading-edge performance to ASIC customers.
Abstract: A library strategy has been developed to enable IBM Microelectronics ASIC development to keep pace with rapid technology enhancements and to offer leading-edge performance to ASIC customers. Library elements are designed using migratable design rules to allow designs to be reused in future advanced technologies; and library contents, design methodology, test methodology, and packaging offerings for the ASICs also are consistent between current and future technologies. The benefit to the ASIC customer is an ASIC with a rich library of logic functions, arrays, and I/Os for today's designs, and with a ready migration path into future designs.
Citations
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01 Nov 1998
TL;DR: A comprehensive approach to accurately characterize the device and interconnect characteristics of present and future process generations is described, resulting in the generation of a representative strawman technology that is used in conjunction with analytical model simulation tools and empirical design data to obtain a realistic picture of the future of circuit design.
Abstract: We take a fresh look at the problems posed by deep submicron (DSM) geometries and re-open the investigation into how DSM effects are most likely to affect future design methodologies. We describe a comprehensive approach to accurately characterize the device and interconnect characteristics of present and future process generations. This approach results in the generation of a representative strawman technology that is used in conjunction with analytical model simulation tools and empirical design data to obtain a realistic picture of the future of circuit design. We then proceed to quantify the precise impact of interconnect, including delay degradation due to noise, on high performance ASIC designs. Having determined the role of interconnect in performance, we then reconsider the impact of future processes on ASIC design methodology.
322 citations
01 Apr 2001
TL;DR: A comprehensive approach to accurately characterizing the device and interconnect characteristics of present and future process generations is described and the precise impact of interconnect, including dynamic delay due to noise, on the performance of high-end integrated circuit designs is quantified.
Abstract: Process effects in deep-submicrometer geometries are expected to change the physical organization, or microarchitecture, of integrated circuits. The factor that is expected to primarily impact integrated circuit microarchitectures is increasing delays in interconnect. We believe that, to properly microarchitect integrated circuits in small process geometries, it is necessary to get as detailed a picture as possible of the effects and then to draw conclusions about changes in microarchitecture. To this end, in this paper we describe a comprehensive approach to accurately characterizing the device and interconnect characteristics of present and future process generations. This approach uses a detailed extrapolation of future process technologies to obtain a realistic view of the future of circuit design. We then proceed to quantify the precise impact of interconnect, including dynamic delay due to noise, on the performance of high-end integrated circuit designs. Having determined this, we then reconsider the impact of future processes on integrated-circuit design methodology. We determine that local interconnect effects can be managed through a deep-submicrometer design hierarchy that uses 50 K-100 K gate modules as primitive building blocks. In light of this new system-on-a-chip microarchitecture, we then examine global interconnect issues. Our results indicate that, while global communication speeds will necessarily be lower than local clock speeds, international Technology Roadmap for Semiconductors expectations should be attainable to the 0.05-/spl mu/m technology generation. Achieving these high clock speeds (10 GHz local clock) will be aided by the use of a newly proposed routing hierarchy that limits interconnect effects at each level of a design (local, isochronous, and global). In addition, key components of the interconnect architecture of the future include fat (or unscaled) global wires, intelligent repeater and shield wire insertion, and efficient packaging technologies.
136 citations
Cites background or methods from "Technology-migratable ASIC library ..."
...Next, the fan-out of the gates is varied from 1 to 4 (fan-outs greater than 4 are not of practical interest)....
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...Aside from memory elements, the modules, such as branch-prediction units, integer execution units, and reorder units, were each under 100K gates. as microprocessor cores or MPEG decompression units will fit within 100K gates....
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IBM1
TL;DR: The architecture described enables the creation of multiple SoC ASIC designs from a common infrastructure that addresses silicon integration, electrical robustness, and packaging challenges and an implementation strategy follows from this design infrastructure that includes hierarchical design concepts, placement, routing, and verification processes.
Abstract: The density and performance of advanced silicon technologies have made system-on-a-chip ASICs possible. SoCs bring together a diverse set of functions and technology features on a single die of enormous complexity. The physical design of these complex ASICs requires a rich set of functional elements that integrate efficiently with a set of design flows and tools productive enough to meet product requirements successfully, without consuming more time or design resources than a simpler design. The architecture described, including functional libraries and physical design conventions, enables the creation of multiple SoC ASIC designs from a common infrastructure that addresses silicon integration, electrical robustness, and packaging challenges. An implementation strategy follows from this design infrastructure that includes hierarchical design concepts, placement, routing, and verification processes.
22 citations
18 Jan 1999
TL;DR: It is found that most of the errors can be uncovered by making use of these two benchmark circuits to port the underlying cell library to the target environment.
Abstract: The experience of designing and employing two benchmark circuits to improve the quality of a standard cell library is reported. It is found that most of the errors can be uncovered by making use of these two benchmark circuits to port the underlying cell library to the target environment. Two releases of a 0.25 /spl mu/m standard cell library have been tested by these two benchmark circuits to ensure their quality.
8 citations
Cites background from "Technology-migratable ASIC library ..."
...However, with ever increasing availability of semiconductor foundry and commercial CAD tools to the university community and advancement in cell-based synthesis technology, more activities in cell library design within university community [9-11] have been carried out....
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IBM1
TL;DR: An integrated computer-aided design (CAD) framework for evaluating MOSFET and layout parasitic extraction (LPE) models and circuit simulators used in the timing and power analysis of CMOS products is presented and builds a step-wise understanding of the underlying parameter values in the models and their impact on circuit performance.
Abstract: An integrated computer-aided design (CAD) framework for evaluating MOSFET and layout parasitic extraction (LPE) models and circuit simulators used in the timing and power analysis of CMOS products is presented. This unified CAD methodology builds a step-wise understanding of the underlying parameter values in the models and their impact on circuit performance. A number of circuit experiments are included to extract the contributions of key MOSFET parameters and physical layout sensitive parasitic elements from circuit simulation results. This CAD setup thus allows easy and detailed comparison of different technologies, device models, and LPE tools to prevent possible bugs in the software as well as inaccuracies in device and parasitic models and timing tools. The software code to carry out the circuit simulations, analysis, and display of the results in an automated fashion has been specifically developed to support this framework. Some of the experiments designed for this work are also placed on the product chip for model-to-hardware correlation. The comparison of the hardware data to the model predictions points to the sources of any discrepancies and aids in tuning the product design to reflect changes in the technology as part of an overall design for manufacturing (DFM) platform
6 citations
Cites methods from "Technology-migratable ASIC library ..."
...For standard-cell based ASIC design methodology [18], a library of standard cells is characterized using a SPICE-like circuit simulator [19]–[ 22 ]....
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References
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IBM1
TL;DR: The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBM's high-density CMOS ASIC (application-specific integrated circuit) logic components is described.
Abstract: The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBM's high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The tester's design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in each component design, built-in self-test logic within embedded memory arrays, and the use of weighted random-pattern logic testing. The development of the tester hardware is discussed, and capital costs of the new tester are compared with those of other approaches. >
50 citations
IBM1
TL;DR: A boundary-scan logic design method that depends only on level-sensitive scan design (LSSD) principles has been developed for IBM CMOS application-specific integrated circuit (ASIC) products.
Abstract: A boundary-scan logic design method that depends only on level-sensitive scan design (LSSD) principles has been developed for IBM CMOS application-specific integrated circuit (ASIC) products. This technique permits comprehensive testing of LSSD ASICs with high signal input/output (I/O) pin counts, using relatively inexpensive reduced-pin-count automatic test equipment (ATE). This paper describes the LSSD logic structures required, the reduced-pin-count testing and burn-in processes used, and the ASIC product design decisions that must be made to establish a consistent boundary-scan implementation.
49 citations
IBM1
37 citations
IBM1
TL;DR: This paper describes the IBM ASIC design methodology, and focuses on the key areas of the methodology that enable a customer to exploit the technology in terms of performance, density, and testability, all in a fast-time-to-market ASIC paradigm.
Abstract: The IBM ASIC design methodology enables a product developer to fully incorporate the high-density, high-performance capabilities of the IBM CMOS technologies in the design of leading-edge products. The methodology allows the full exploitation of technology density, performance, and high testability in an ASIC design environment. The IBM ASIC design methodology builds upon years of experience within IBM in developing design flows that optimize performance, testability, chip density, and time to market for internal products. It has also been achieved by using industry-standard design tools and system design approaches, allowing IBM ASIC products to be marketed externally as well as to IBM internal product developers. This paper describes the IBM ASIC design methodology, and then focuses on the key areas of the methodology that enable a customer to exploit the technology in terms of performance, density, and testability, all in a fast-time-to-market ASIC paradigm. Also emphasized are aspects of the methodo logy that allow IBM to market its design experience and intellectual property.
22 citations
IBM1
TL;DR: Metallization and device channel length enhancements to an existing 0.5-/spl mu/m CMOS process are exploited in the design of a high-density ASIC (application-specific integrated circuit) logic family.
Abstract: Metallization and device channel length enhancements to an existing 0.5-/spl mu/m CMOS process are exploited in the design of a high-density ASIC (application-specific integrated circuit) logic family. Wired circuit density exceeds one-million equivalent two-input NANDs, with typical gate delays of 250 ps at 3.3 V. A total of 17 different chip sizes are offered, along with several surface-mount package options. Both IBM and industry-standard design systems are supported, along with a cost effective LSSD-based test methodology.
18 citations