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Test Data Compression Using Selective Encoding of Scan Slices

01 Nov 2008-IEEE Transactions on Very Large Scale Integration Systems (IEEE)-Vol. 16, Iss: 11, pp 1429-1440

TL;DR: A selective encoding method that reduces test data volume and test application time for scan testing of intellectual property (IP) cores and derives a probabilistic lower bound on the compression for a given care-bit density.

AbstractWe present a selective encoding method that reduces test data volume and test application time for scan testing of intellectual property (IP) cores. This method encodes the slices of test data that are fed to the scan chains in every clock cycle. To drive N scan chains, we use only c tester channels, where c=lceillog2(N+1)rceil+2 . In the best case, we can achieve compression by a factor of N/c using only one tester clock cycle per slice. We derive a sufficient condition on the distribution of care bits that allows us to achieve the best-case compression. We also derive a probabilistic lower bound on the compression for a given care-bit density. Unlike popular compression methods such as embedded deterministic test (EDT), the proposed approach is suitable for IP cores because it does not require structural information for fault simulation, dynamic compaction, or interleaved test generation. The on-chip decoder is small, independent of the circuit under test and the test set, and it can be shared between different circuits. We present compression results for a number of industrial circuits and compare our results to other recent compression methods targeted at IP cores.

Topics: Data compression (60%), Automatic test pattern generation (59%), Test data (57%), Test method (54%), Test set (51%)

Summary (2 min read)

Introduction

  • In the best case, the authors can achieve compression by a factor of using only one tester clock cycle per slice.
  • Recent growth in design complexity and the integration of embedded cores in system-on-chip (SoC) ICs has led to a tremendous growth in test data volume; industry experts predict that this trend will continue over the next few years [5].
  • The number of ATE channels that can directly drive scan chains is limited due to pin count constraints.
  • These compression schemes exploit the fact that scan test vectors typically contain a large fraction of unspecified bits even after compaction.

II. PROPOSED APPROACH

  • As shown in Fig. 1, the proposed approach encodes the slices of test data (scan slices) that are fed to the internal scan chains.
  • The first data code refers to bit 0 (first bit of group 0), and the second data code carries the content of group 0.
  • Control codes 00, 01, and 10 indicate that the current slice code is a single-bit mode slice code, and control code 11 indicates the current slice code is a groupcopy mode slice code.
  • As discussed before, two group-copy mode slice codes are needed to encode a given group, one to indicate the starting bit of the group, and the other to carry the content of the group.

A. Upper and Lower Bounds on Compression

  • By deriving the upper and lower bounds on compression, this section provides more insights into the proposed compression method.
  • Such methods, however, require structural information about the circuit.
  • The lower bound can be expressed in terms of care-bit density.
  • The number of target symbols in any scan slice can therefore be viewed as a random variable that follows a binomial distribution, i.e., Each target symbol in a scan slice must be mapped to one slice code, hence, the average number of slice codes for a given scan slice is .

B. ATE Pattern Repeat

  • A property of the proposed compression method is that consecutive -bit compressed slices fed by the ATE are often identical or compatible.
  • Therefore, ATE pattern repeat can be used to further reduce test data volume after selective encoding of scan slices.
  • With ATE pattern repeat, these slice codes can be further compacted.
  • The example shows Authorized licensed use limited to: DUKE UNIVERSITY.

III. DECOMPRESSION ARCHITECTURE

  • Fig. 7 shows the state transition diagram of the decoder.
  • The signal , when asserted to 0, resets the FSM to its initial state.
  • TABLE II FIVE GROUPS OF OPERATIONS FOR THE DECODER Fig. Fig. 9. One bit of the buffer. may contain less bits).
  • Therefore, in the group-copy mode, additional combinational logic is needed to address the other bits together with the first bit.

IV. EXPERIMENTAL RESULTS

  • The authors apply the proposed approach to eight representative industrial circuits.
  • Table III describes these circuits and the corresponding test sets.
  • Table IV shows the compression results obtained using the proposed method for the different test cases.
  • Therefore, the proposed method can achieve significant reduction in data volume over ATPG-compacted test sets.
  • The authors compared the two methods for the same values of , the number of ATE channels.

V. CONCLUSION

  • The authors have presented a test data compression technique for designs with multiple scan chains.
  • This method does not require detailed structural information about the CUT, and utilizes a generic on-chip decoder that is independent of the CUT and the test set.
  • While the hardware overhead depends on the number of internal scan chains, the authors have seen that for an industrial circuit with over 1-M gates, the overhead is only 1% for as many as 1024 internal scan chains.
  • The clock inputs of these scan cells need to be appropriately gated so that they can be triggered separately from other cells in the same scan chain.
  • Experimental results for eight industrial circuits show that compared to dynamically compacted test sets, up to 28 reduction in test data volume and 20 reduction in test application time can be obtained.

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 11, NOVEMBER 2008 1429
Test Data Compression Using Selective
Encoding of Scan Slices
Zhanglei Wang, Member, IEEE, and Krishnendu Chakrabarty, Fellow, IEEE
Abstract—We present a selective encoding method that reduces
test data volume and test application time for scan testing of In-
tellectual Property (IP) cores. This method encodes the slices of
test data that are fed to the scan chains in every clock cycle. To
drive
scan chains, we use only tester channels, where
=
log
2
( +1) +2
. In the best case, we can achieve compression
by a factor of
using only one tester clock cycle per slice. We
derive a sufficient condition on the distribution of care bits that
allows us to achieve the best-case compression. We also derive a
probabilistic lower bound on the compression for a given care-bit
density. Unlike popular compression methods such as Embedded
Deterministic Test (EDT), the proposed approach is suitable for IP
cores because it does not require structural information for fault
simulation, dynamic compaction, or interleaved test generation.
The on-chip decoder is small, independent of the circuit under test
and the test set, and it can be shared between different circuits. We
present compression results for a number of industrial circuits and
compare our results to other recent compression methods targeted
at IP cores.
Index Terms—ATE pattern repeat, IP cores, scan slice, test data
compression.
I. INTRODUCTION
T
EST DATA volume is now recognized as a major contrib-
utor to the cost of manufacturing testing of integrated cir-
cuits (ICs) [1]–[4]. Recent growth in design complexity and the
integration of embedded cores in system-on-chip (SoC) ICs has
led to a tremendous growth in test data volume; industry experts
predict that this trend will continue over the next few years [5].
For example, the 2005 ITRS document predicted that the test
data volume for integrated circuits will be as much as 30 times
larger in 2010 than in 2005 [6].
High test data volume leads to an increase in testing time.
In addition, high test data volume may also exceed the lim-
ited memory depth of automatic test equipment (ATE). Mul-
tiple ATE reloads are time consuming because data transfers
from a workstation to the ATE hard disk, or from the ATE hard
disk to ATE channels are relatively slow; the upload time ranges
from tens of minutes to hours [7]. Test application time for scan
Manuscript received January 13, 2007; revised September 3, 2007. First pub-
lished August 12, 2008; current version published October 22, 2008. This work
was supported in part by the National Science Foundation under Grant CCR-
0204077. A preliminary version of this paper was published in the Proceeding
of the IEEE International Test Conference, pp. 581590, 2005. This research was
carried out when Zhanglei Wang was a Ph.D. student at Duke University.
Z. Wang was with the Department of Electrical and Computer Engineering,
Duke University, Durham, NC 27708 USA. He is now with Cisco Systems Inc.,
San Jose, CA 95134 USA (e-mail: zhawang@cisco.com).
K. Chakrabarty is with the Department of Electrical and Computer Engi-
neering, Duke University, Durham, NC 27708 USA (e-mail: krish@duke.edu).
Digital Object Identifier 10.1109/TVLSI.2008.2000674
testing can be reduced by using a large number of internal scan
chains. However, the number of ATE channels that can directly
drive scan chains is limited due to pin count constraints.
Logic built-in self-test (LBIST) [8] has been proposed as a
solution for alleviating these problems. LBIST reduces depen-
dencies on expensive ATEs and allows precomputed test sets to
be embedded in test sequences generated by BIST hardware to
target random pattern resistant faults. However, the memory re-
quired to store the top-up patterns for LBIST can exceed 30% of
the memory used in a conventional automatic test pattern gener-
ation (ATPG) approach [8]. With increasing circuit complexity,
the storage of an extensive set of ATPG patterns on-chip be-
comes prohibitive [1]. Moreover, BIST can be applied directly
to SoC designs only if the embedded cores are BIST-ready; con-
siderable redesign may be necessary for incorporating BIST in
cores that are not BIST-ready.
Test data compression offers a promising solution to the
problem of increasing test data volume. A test set
for the
circuit under test (CUT) is compressed to a much smaller data
set
, which is stored in ATE memory. An on-chip decoder
is used to generate
from during test application. A
popular class of compression schemes relies on the use of a
linear decompressor. These techniques are based on LFSR
reseeding [9]–[12] and combinational linear expansion net-
works consisting of
XOR gates [13]–[15], and they have been
implemented in commercial tools such as TestKompress from
Mentor Graphics [1], SmartBIST from IBM/Cadence [3],
and DBIST from Synopsys [16]. These compression schemes
exploit the fact that scan test vectors typically contain a large
fraction of unspecified bits even after compaction. However,
the on-chip decoders for these techniques are specific to the
test set, which necessitates decompressor redesign if the test set
changes during design iterations. Finally, in order to achieve
the best compression, these methods resort to fault simulation
and test generation. As a result, they are less suitable for test
reuse in SoC designs based on Intellectual Property (IP) cores.
Another category of compression methods uses statistical
coding, variants of run-length coding, dictionary-based coding,
and hybrid techniques [17]–[22]. These methods exploit the
regularity inherent in test data to achieve high compression.
However, most of these schemes target single scan chains and
they require synchronization between the ATE and CUT.
We present a selective encoding method that reduces test data
volume and test application time for the scan testing of IP cores.
This method encodes the slices of test data that are fed to the
scan chains in every clock cycle. Unlike many prior methods,
the proposed method does not encode all the specified (0 s and
1 s) and unspecified (don’t care) bits in a slice. For example, if
a slice contains more 1’s than 0’s, only the 0’s are encoded and
all don’t cares are mapped to 1. We use only
tester channels,
1063-8210/$25.00 © 2008 IEEE
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1430 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 11, NOVEMBER 2008
where , to drive scan chains. The log-
arithmic reduction in the number of tester channels allows us to
use a large number of internal scan chains, thereby reducing test
application time significantly. In the best case, we can achieve
compression by a factor of
using only one tester clock cycle
per slice. We derive a sufficient condition on the distribution of
care bits that allows us to achieve the best-case compression.
We also present a probabilistic lower bound on the compression
for a given care bit density.
The proposed technique does not require dedicated test pins
for each core in an SoC. If cores are tested sequentially, only
one common test interface is needed. If some cores are tested
in parallel, then they can together be viewed as a larger core
with more scan chains. For example, if five cores are tested in
parallel, and each core has 255 scan chains, it is equivalent to
one core with 255
5 scan chains. The proposed technique will
therefore only require 13 pins. Meanwhile, the on-chip decoder
must be modified to handle the scan-in and capture for the five
different cores.
The pattern decompression is of the continuous-flow type be-
cause no complex handshakes are required between the tester
and the chip, and there is no need to introduce tester stall cy-
cles. Unlike popular compression methods, such as Embedded
Deterministic Test (EDT) [1], the proposed approach is suitable
for IP cores because it does not require structural information for
fault simulation, dynamic compaction, or interleaved test gen-
eration. The on-chip decoder is small, independent of the circuit
under test and the test set. We present compression results for a
number of industrial circuits, and compare our results to other
recent compression methods targeted at IP cores.
The steady increase in clock frequencies over recent years has
led to designs with a small number of gates between latches, or
between latches and input/output (I/O) pins [23]. As a result,
logic circuits today have very short combinational logic depth,
and many logic cones with very little overlap. This is in contrast
to older circuits such as the ISCAS’85 benchmarks that tend
to have a smaller number of overlapping logic cones. A conse-
quence of the shallow logic depth is that test patterns in present
day circuits contain many don’t care bits; e.g., it has been re-
ported recently that test sets for industrial circuits contain only
1%–5% care bits [24]. After a desired stuck-at coverage is ob-
tained (using methods such as dynamic compaction and fault
grading to reduce pattern count), a commercial test pattern gen-
erator typically uses random fill to increase the likelihood of
surreptitious detection of unmodeled faults. However, if the test
sets for the cores are delivered with the don’t care bits to the
system integrator, an appropriate compression method can be
used at the system level to reduce test data volume and testing
time. This imposes no additional burden on the core vendor. Un-
modeled faults can still be detected if the compression method
does not arbitrarily map all don’t cares to either 1’s or 0’s.
We do not address the problem of output compaction in this
paper. The proposed input compression method can be used
with recent output compaction methods such as X-compact [2],
convolutional compaction [25], and i-compact [26] to further re-
duce test data volume.
The rest of this paper is organized as follows. The details of
the proposed approach are described in Section II. Section III
presents the decompression architecture and Section IV presents
compression results for industrial circuits.
Fig. 1. Test application using the proposed approach.
Fig. 2. Slice-code consists of a 2-bit control-code and a
K
-bit data code.
II. P
ROPOSED APPROACH
As shown in Fig. 1, the proposed approach encodes the slices
of test data (scan slices) that are fed to the internal scan chains.
The on-chip decoder contains an
-bit buffer, and it manipu-
lates the contents of the buffer according to the compressed data
that it receives. After all the compressed data for a single slice
is received, the data in the buffer is delivered to the scan chains.
Each slice is encoded as a series of
-bit slice-codes, where
, , and is the number of internal
scan chains in the CUT. The number of slice codes needed to
encode a given slice depends on the distribution of 1’s, 0’s, and
don’t cares in the slice. As shown in Fig. 2, the first two bits
of a slice-code form the control-code that determines how the
following
bits, referred to as the data-code, are interpreted.
As described in Section I, the proposed approach only en-
codes a subset of the specified bits in a slice. First, the encoding
procedure examines the slice and determines the number of 0-
and 1-valued bits. If there are more 1’s (0’s) than 0’s (1’s), then
all X’s in this slice are mapped to 1 (0), and only 0’s (1’s) are
encoded. The 0’s (1’s) are referred to as target-symbols and are
encoded into data-codes in two modes: 1) single-bit-mode and
2) group-copy-mode.
In the single-bit-mode, each bit in a slice is indexed from 0
to
. A target-symbol is represented by a data-code that
takes the value of its index. For example, to encode the slice
XXX10000, the X’s are mapped to 0 and the only target symbol
of 1 at bit position 3 is encoded as 0011. In this mode, each target
symbol in a slice is encoded as a single slice code. Obviously,
if there are many target symbols that are adjacent or near to
each other, it is inefficient to encode each of them using separate
slice codes. Hence, the group-copy mode has been designed to
increase compression efficiency.
In the group-copy mode, an
-bit slice is divided into
groups, and each group (with the possible exception
of the last group) is
-bits wide, as shown in Fig. 3. The
groups are numbered from 0 to , with the first group
(referred to as group 0) containing bits 0 to
and so on.
If a given group contains more than one target symbol, then the
group-copy mode is used and the entire group is copied to a
data code. Two data codes are needed to encode a group. The
first data code specifies the index of the first bit of the group,
and the second data code contains the actual data. In the group-
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WANG AND CHAKRABARTY: TEST DATA COMPRESSION USING SELECTIVE ENCODING OF SCAN SLICES 1431
TABLE I
E
XAMPLE TO
ILLUSTRATE
SLICE ENCODING
Fig. 3.
N
-bit scan slice is divided into
M
=
d
N=K
e
groups in the group-copy
mode.
copy mode, don’t cares can be randomly filled instead of being
mapped to 0 or 1 by the compression scheme.
For example, let
and , i.e.,
each slice is 31-bits wide and consists of six 5-bit
groups and one 1-bit group. To encode the slice
X1110_00000_XX00X_XXXX0_00000_00XXX_0
(the slice is shown separated by underscores into 5-bit groups),
only the three 1’s in group 0 are encoded. Since group 0 has
more than one target symbol, the group-copy mode is used,
yielding two data codes 00000 and X1110. The first data code
refers to bit 0 (first bit of group 0), and the second data code
carries the content of group 0.
The concept of a group is relevant only for the group-copy-
mode. If only the single-bit mode is used, we do not need to con-
sider groups at all. The underlying idea for the proposed method
is: 1) only encode target symbols; 2) the bit-index of the target
symbol is encoded in the slice code for proper decompression;
3) to further improve encoding efficiency, the group-copy mode
is introduced, in which the scan slice is divided into groups.
Since data codes are used in both modes, control codes are
needed to avoid ambiguity. Control codes 00, 01, and 10 indi-
cate that the current slice code is a single-bit mode slice code,
and control code 11 indicates the current slice code is a group-
copy mode slice code. The first slice code for any scan slice is
always a single-bit mode code, and its control code can only be
00 or 01. Hence, control codes 00 and 01 are referred to as
ini-
tial-control codes and they indicate the start of a new slice. Con-
trol code 00 (01) indicates that all X’s in the current scan slice
should be mapped to 0 (1), and the target symbol for the whole
slice is 1 (0). Except the first slice code, all other single-bit mode
slice codes for the same scan slice can only have the control
code 10, i.e., simply setting the bit specified by the associated
data code to the target symbol of this slice.
Table I shows a complete example to further illustrate how
scan slices are encoded into slice codes. In this example,
and . In Case 1, the slice contains only one
target symbol (1), and is encoded into one slice-code using the
single-bit mode. In Case 2, the slice contains no target symbols.
To handle this special case, we introduce a dummy data code
whose value is
. Since the bits in the scan slice is indexed
from 0 to
, a data code with value implies that no bit
should be set to the target symbol.
In Case 3 and Case 4, the same slice is encoded with the
group-copy mode turned off and on, respectively. In Case 3,
since the slice contains six target symbols, six single-bit mode
slice codes are required to encode it, resulting in negative com-
pression, which is undesirable. In Case 4, however, only four
slice codes are needed: three group-copy mode slice codes to
encode groups 0 and 1, and one single-bit mode slice code to
encode the 1 at bit 30.
As discussed before, two group-copy mode slice codes are
needed to encode a given group, one to indicate the starting bit
of the group, and the other to carry the content of the group.
However, to further improve compression efficiency, if
adjacent groups are to be encoded using the group-copy mode,
they can be merged together. This optimization procedure is
referred to as group merging. As shown in Case 4, since groups
0 and 1 are adjacent, instead of using four slice codes 1100000,
11X1100, 1100101, and 1101101 to encode the two groups,
only three slice codes are needed. The code that indicates
the starting bit of group 1 (1100101) is omitted. Therefore,
to encode
adjacent groups, group-copy mode
slice codes are needed, with the first slice code indicating
the starting bit of the first group, and the other
group-copy
mode slice codes carrying the contents of the
groups. With
group merging, the number of consecutive group-copy mode
slice codes is no longer fixed. To avoid ambiguity, two series
of consecutive group-copy mode slice codes that encode two
series of adjacent groups must be interleaved by one single-bit
mode slice code.
Cases 3 and 4 also show that the group-copy mode should be
used whenever possible. Since two group-copy mode slice codes
are sufficient to encode any
-bit group, if a group contains
more than one target symbol, it should be encoded using the
group-copy mode.
The encoding procedure is summarized in Fig. 4. In Step 1),
each test vector is divided into a series of slices. We then encode
each slice as a series of slice codes. In Steps 3)–7), the numbers
of 0’s and 1’s are calculated, and the target symbol as well as
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1432 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 11, NOVEMBER 2008
Fig. 4. Encoding procedure.
the control code of the first slice code are set. The first slice code
of each slice must contain an initial-control code (00 or 01).
Steps 8)–14) encode all the groups of a slice. For each group
of a slice, if it contains more than one target symbol, it is
encoded using the group-copy mode; otherwise, it is encoded
using the single-bit mode.
Once all groups have been encoded, the slice code gener-
ation step (Step 15) becomes straightforward. It first merges
group-copy mode slice codes that correspond to adjacent
groups, and then appropriately interleaves group-copy mode
slice codes with single-bit mode slice codes. It also ensures that
the first slice code is a single-bit mode code.
As can be seen from Fig. 4, the encoding procedure consists
of two nested loops: the outer loop is for scan slices, and the
inner loop is for groups of a given slice. Hence, its time com-
plexity is
, where is the total data volume
of the test set in bits.
A. Upper and Lower Bounds on Compression
By deriving the upper and lower bounds on compression,
this section provides more insights into the proposed compres-
sion method. The maximum compression is achieved when each
slice is encoded as a single slice code. Hence, the upper bound
on compression is simply
, where is the number of scan
chains and
is the number of ATE channels.
The upper bound can only be achieved if every slice is en-
coded as a single slice code. This, in turn, is only possible if
every scan slice contains either zero or one target symbol. How-
ever, the maximum compression factor of
can be achieved
even if the test set contains a large fraction of care bits. Test set
relaxation methods as in [27] can be used to help approach the
upper bound. Such methods, however, require structural infor-
mation about the circuit.
To derive the lower bound, we do not consider the group-
copy mode. Note that the outcome of the group-copy mode de-
pends on the actual distribution of the target symbols in scan
slices. It is not possible to derive a bound that considers the
group-copy mode, but is independent of the distribution of the
target symbols. Since the target symbol distribution is difficult
to model and it usually changes from slice-to-slice, such an
analysis is rather difficult. Moreover, the optimization step that
merges consecutive group-copy mode slice codes further makes
the analysis even more difficult.
The lower bound is reached when each target symbol is en-
coded into a single-bit mode slice code, i.e., each group contains
at most one target symbol such that the group-copy mode is not
used for the entire test set. The lower bound can be expressed in
terms of care-bit density. Let the fraction of 1’s, 0’s, and don’t
cares in any scan slice be
, , and , respectively. The prob-
ability
that any bit in the scan slice is a target symbol is given
by
. The number of target symbols in any scan
slice can therefore be viewed as a random variable
that fol-
lows a binomial distribution, i.e.,
The expected number of target symbols is simply .
Each target symbol in a scan slice must be mapped to one slice
code, hence, the average number of slice codes for a given scan
slice is
. If we ignore the additional compression that can be
obtained using the group-copy mode, and let
be the number of
scan slices, we get the following expression for the compression
factor
:
(1)
Note that even if we do not assume any knowledge of
and
, a lower bound can be obtained from the knowledge of
the care-bit density, i.e.,
. If the care-bit density
for each scan slice is different, i.e., the care-bit densities are
for the scan slices, respectively, we get
(2)
Equation (2) provides a more accurate bound because the first
few pattern in a (ordered) test set contain many more care bits
than the latter patterns. However, computing this lower bound
requires nearly as much effort as compressing the test set.
Fig. 5 shows the probabilistic lower bound on the compres-
sion factor
for different values of and . The lower bound
decreases with increasing
, since increases with . In prac-
tice, due to the use of the group-copy mode, we often achieve a
larger compression factor. Thus, while the upper bound is overly
optimistic for larger values of
, the lower bound is overly pes-
simistic for larger values of
.
B. ATE Pattern Repeat
A property of the proposed compression method is that con-
secutive
-bit compressed slices fed by the ATE are often iden-
tical or compatible. Therefore, ATE pattern repeat can be used to
further reduce test data volume after selective encoding of scan
slices. In the uncompressed data sets, especially among the test
vectors that lie near the end of a test set, there are a large number
of consecutive slices that contain no target symbols. These slices
are encoded as identical single slice codes that have only dummy
data codes. With ATE pattern repeat, these slice codes can be
further compacted. Additionally, consecutive group-copy mode
slice codes can also be compacted if they are compatible. Fig. 6
shows how a set of scan slices are encoded. The example shows
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WANG AND CHAKRABARTY: TEST DATA COMPRESSION USING SELECTIVE ENCODING OF SCAN SLICES 1433
Fig. 5. Lower bounds on the compression factor for different values of
N
and
p
.
Fig. 6. Encoding example.
that some slice codes, e.g., the first two in the encoded test set,
can be combined and applied using ATE pattern repeat.
III. D
ECOMPRESSION
ARCHITECTURE
Fig. 7 shows the state transition diagram of the decoder. The
decoder enters designated states and performs different opera-
tions as specified by the control codes that it receives. Initially,
the decoder is in the init state; when it receives an initial-con-
trol code, it enters the single-bit mode and performs a series of
operations referred to as P1. Table II explains the five groups of
operations (P1–P5) in Fig. 7.
Fig. 8 shows the block diagram of the decoder. The finite-state
machine (FSM) generates control signals for the other com-
ponents. The
-bit address register is used in the group-copy
mode to store the index of the first bit of the target group. This
register can be incremented by
to address a series of adjacent
groups. The
-to- address decoder generates selection sig-
nals to address a single bit of the buffer. The
-bit buffer con-
tains combinational logic that provides the following function-
alities: 1) each bit in the buffer can be individually addressed and
2) all bits in the same group can be addressed in parallel. These
two functions are used in the single-bit mode and the group-copy
mode, respectively.
Fig. 7. State transition diagram of the decoder.
The 2-bit input signal is the control-code from the
tester. The signal
, when asserted to 0, resets the FSM to
its initial state. The signal
is set to high when the decoding
process for a slice is finished and the content of the buffer is
shifted to the internal scan chains.
If the signal
is asserted, the decoder works in the
group-copy mode. The
is used to increment the ad-
dress register by
. In the group-copy mode, the -to- ad-
dress decoder receives input from the address register; in the
single-bit-mode, it receives input from the data-code input. The
-bit selection signal is used to address a single bit in the
buffer. At any given time only one of the
wires is asserted.
The second bit of the control code
, i.e., the target
symbol, is latched to
. In the single-bit mode, the specified bit
is set to
. If the control code is 00 or 01, the signal
is asserted, and all other bits except the specified bit are set to
the complement of
. The signal is asserted whenever
the buffer contents are to be changed. The signal
is set to 0
only during the first clock cycle of the group-copy mode; at the
same time the address of the first bit of the group is loaded to
the address register.
The
signal from the address decoder can only address a
single bit of the buffer. However, in the group-copy mode, all
the
bits in the target group should be addressed (the last group
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Citations
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Journal ArticleDOI
TL;DR: A new test data compression method for intellectual property (IP) cores testing, based on the reuse of parts of dictionary entries, is presented, supported with extensive simulation results and comparisons to already known testData compression methods suitable for IP cores testing.
Abstract: In this paper, we present a new test data compression method for intellectual property (IP) cores testing, based on the reuse of parts of dictionary entries. Two approaches are investigated: the static and the dynamic. In the static approach, the content of the dictionary is constant during the testing of a core, while in the dynamic approach the testing of a core consists of several test sessions and the content of the dictionary is different during each test session. The efficiency of the proposed method is supported with extensive simulation results and comparisons to already known test data compression methods suitable for IP cores testing.

25 citations


Cites background from "Test Data Compression Using Selecti..."

  • ...Therefore we have four categories: fixed-to-fixed [2], [3], fixed-to-variable [4]–[13], variable-to-fixed [14]–[17], and variable-to-variable [18]–[32]....

    [...]

  • ...They are based on the fact that even in compacted test sets the percentage of unspecified bits is large [1], [17]....

    [...]


Journal ArticleDOI
TL;DR: A new scan architecture is proposed to compress test stimulus data, compact test responses, and reduce test application time for launch-on-capture (LOC) delay testing.
Abstract: Test data compression is a much more difficult problem for launch-on-capture (LOC) delay testing, because test data for LOC delay testing is much more than that of stuck-at fault testing, and LOC delay fault test generation in the two-frame circuit model can specify many more inputs. A new scan architecture is proposed to compress test stimulus data, compact test responses, and reduce test application time for LOC delay fault testing. The new scan architecture merges a number of scan flip-flops into the same group, where all scan flip-flops in the same group are assigned the same values for all test pairs. Sufficient conditions are presented for including any pair of scan flip-flops into the same group for LOC transition, non-robust path delay, and robust path delay fault testing. Test data for LOC delay testing based on the new scan architecture can be compressed significantly. Test application time can also be reduced greatly. Sufficient conditions are presented to construct a test response compactor for LOC transition, non-robust, and robust path delay fault testing. Folded scan forest and test response compactor are constructed for further test data compression. Sufficient experimental results are presented to show the effectiveness of the method.

22 citations


Cites methods or result from "Test Data Compression Using Selecti..."

  • ...We also compare our method with the Illinois scan [Shah and Patel 2001] and selective encoding [Wang and Chakrabarty 2008] on stimulus test data volume for the IWLS2005 circuits....

    [...]

  • ...…1.32 vga 32 17079 9211 44947048 8297 23459759 9500385 10907846 6.04 6.89 21.14 40.50 10.16 In Tables VI and VIII, we present a comparison of the proposed method with the Illinois scan [Shah and Patel 2001] and selective encoding [Wang and Chakrabarty 2008] on stimulus data volume compression....

    [...]

  • ...As shown in Tables VII and VIII, FFs and faults represent the number of scan .ip-.ops and the number of transition faults....

    [...]

  • ...It is found that the proposed method obtains much less stimulus data volume, as compared to the Illinois scan [Shah and Patel 2001] and selective encoding [Wang and Chakrabarty 2008] for the ISCAS89 circuits....

    [...]

  • ...Performance of Scan Flip-Flop Grouping Scheme in Xiang et al. [2007a] for LOC Transition Delay Fault Testing cir. faults FFs FC FC new untestable R1 R2 gs s13207 15602 669 82.53 65.48 2661 28.54 30.85 4 s15850 19046 597 78.8 63.1 2991 19.32 22.54 6 s35932 62798 1728 87.2 78.35 5558 0.98 1.14 158 s38417 49738 1636 96.8 84.04 6347 7.11 8.33 20 s38584 61254 1452 90.76 81.27 5814 7.49 9.65 16 usb 76917 1746 96.65 86.43 7861 8.24 8.91 17 pci 118107 3359 97.64 80.26 20527 6.04 7.14 22 des 448789 8808 99.99 92.3 34512 0.55 0.82 327 vga 700141 17079 98.62 85.99 88428 3.32 3.71 40 Table X. Performance of the Folded Scan Forest with Different Numbers of Scan-In Pins circuits case 1 case 2 case 3 Sin R1 R2 TA Sin R1 R2 TA Sin R1 R2 TA s13207 8 27.81 53....

    [...]


Proceedings ArticleDOI
05 Nov 2012
TL;DR: This paper introduces a structured methodology for porting in-system the constrained-random stimuli generation aspect from a pre-silicon verification environment.
Abstract: When generating the verification stimuli in a pre-silicon environment, the primary objectives are to reduce the simulation time and the pattern count for achieving the target coverage goals. In a hardware environment, because an increase in the number of stimuli is inherently compensated by the advantage of real-time execution, the objective augments to considering hardware complexity when designing in-system stimuli generators that must operate according to user-programmable constraints. In this paper we introduce a structured methodology for porting in-system the constrained-random stimuli generation aspect from a pre-silicon verification environment.

12 citations


Journal ArticleDOI
06 Dec 2018
TL;DR: A unified test technique that targets faults in links, routers, and cores of a network-on-chip design based on test sessions and results highlight the effectiveness of the proposed method in reducing test time.
Abstract: We present a unified test technique that targets faults in links, routers, and cores of a network-on-chip design based on test sessions. We call an entire procedure, that delivers test packets to the subset of routers/cores, a test session. Test delivery for router/core testing is formulated as two fault-tolerant multicast algorithms. Test packet delivery for routers is implemented as a fault-tolerant unicast-based multicast scheme via the fault-free links and routers that were identified in the previous test sessions to avoid packet corruption. A new fault-tolerant routing algorithm is also proposed for the unicast-based multicast core test delivery in the whole network. Identical cores share the same test set, and they are tested within the same test session. Simulation results highlight the effectiveness of the proposed method in reducing test time.

9 citations


Cites methods from "Test Data Compression Using Selecti..."

  • ...Scan forest was combined with selective encoding (Wang and Chakrabarty 2008) to compress test data of cores, but the new article uses only scan forest to compress test data inside cores. Therefore, due to the use of different DFT architectures, test data and the test delivery time for the new method are more than that in Xiang (2016a). The cores assigned to the 3D stacked NOCs are different from the ones in this article....

    [...]

  • ...Scan forest was combined with selective encoding (Wang and Chakrabarty 2008) to compress test data of cores, but the new article uses only scan forest to compress test data inside cores. Therefore, due to the use of different DFT architectures, test data and the test delivery time for the new method are more than that in Xiang (2016a). The cores assigned to the 3D stacked NOCs are different from the ones in this article. In the NOCs with four core classes, three core classes, and a single core class, circuits (b19, des, ethernet, vga), (b19, des, vga), and (b19) are randomly assigned, respectively. In this article, des is replaced by netcard for the first two cases, (vga, netcard), (netcard) are randomly assigned for two core classes and a single core class. The above two reasons contribute to the difference in the core test cost between the new method and the one in Xiang (2016a). The fault-tolerant multicast approach for core testing is not affected much by the number of link/router failures....

    [...]

  • ...Scan forest was combined with selective encoding (Wang and Chakrabarty 2008) to compress test data of cores, but the new article uses only scan forest to compress test data inside cores. Therefore, due to the use of different DFT architectures, test data and the test delivery time for the new method are more than that in Xiang (2016a). The cores assigned to the 3D stacked NOCs are different from the ones in this article. In the NOCs with four core classes, three core classes, and a single core class, circuits (b19, des, ethernet, vga), (b19, des, vga), and (b19) are randomly assigned, respectively. In this article, des is replaced by netcard for the first two cases, (vga, netcard), (netcard) are randomly assigned for two core classes and a single core class. The above two reasons contribute to the difference in the core test cost between the new method and the one in Xiang (2016a). The fault-tolerant multicast approach for core testing is not affected much by the number of link/router failures. However, the router testing approach is very sensitive to these failures, which may increases the number of internal router test sessions. As the size of an NOC increases, the new router testing approach becomes less sensitive to the number of failures. The router test cost for the new method is much less than that in Xiang (2016b), because concurrent test delivery and test application for router testing are utilized....

    [...]

  • ...Scan forest was combined with selective encoding (Wang and Chakrabarty 2008) to compress test data of cores, but the new article uses only scan forest to compress test data inside cores....

    [...]


Journal ArticleDOI
TL;DR: The Branch and bound algorithm is used to optimize the constraint satisfaction problem and finds the optimum set of parameter frequency, floor attenuation factor, and path loss coefficient at which the path loss is minimum.
Abstract: Constraint programming is the study of system which is based on constraints. The solution of a constraint satisfaction problem is a set of variable value assignments, which satisfies all members of the set of constraints in the CSP. In this paper the application of constraint satisfaction programming is used in predicting the path loss of various indoor propagation models using chronological backtrack algorithm, which is basic algorithm of CSP. After predicting the path loss at different set of parameters such as frequencies (f), floor attenuation factor (FAF), path loss coefficient (n), we find the optimum set of parameter frequency (f), floor attenuation factor (FAF), path loss coefficient(n) at which the path loss is minimum. The Branch and bound algorithm is used to optimize the constraint satisfaction problem.

5 citations


References
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01 Jan 1991

519 citations


"Test Data Compression Using Selecti..." refers methods in this paper

  • ...These techniques are based on LFSR reseeding [ 9 ]–[12] and combinational linear expansion networks consisting of XOR gates [13]–[15], and they have been implemented in commercial tools such as TestKompress from Mentor Graphics [1], SmartBIST from IBM/Cadence [3], and DBIST from Synopsys [16]....

    [...]

  • ...For example, the 2005 ITRS document predicted that the test data volume for integrated circuits will be as much as 30 times larger in 2010 than in 2005 [ 6 ]....

    [...]


Journal ArticleDOI
TL;DR: This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
Abstract: This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. It is nonintrusive as it does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The EDT scheme consists of logic embedded on a chip and a new deterministic test-pattern generation technique. The main contributions of the paper are test-stimuli compression schemes that allow us to deliver test data to the on-chip continuous-flow decompressor. In particular, it can be done by repeating certain patterns at the rates, which are adjusted to the requirements of the test cubes. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, these schemes result in compression ratios of 30 to 500 times. A comprehensive analysis of the encoding efficiency of the proposed compression schemes is also provided.

500 citations


"Test Data Compression Using Selecti..." refers background or methods in this paper

  • ...With increasing circuit complexity, the storage of an extensive set of ATPG patterns on-chip becomes prohibitive [1]....

    [...]

  • ...Unlike popular compression methods, such as Embedded Deterministic Test (EDT) [1], the proposed approach is suitable for IP cores because it does not require structural information for fault simulation, dynamic compaction, or interleaved test generation....

    [...]

  • ...T EST DATA volume is now recognized as a major contributor to the cost of manufacturing testing of integrated circuits (ICs) [1]–[4]....

    [...]

  • ...These techniques are based on LFSR reseeding [9]–[12] and combinational linear expansion networks consisting of XOR gates [13]–[15], and they have been implemented in commercial tools such as TestKompress from Mentor Graphics [1], SmartBIST from IBM/Cadence [3], and DBIST from Synopsys [16]....

    [...]

  • ...Unlike popular compression methods such as Embedded Deterministic Test (EDT), the proposed approach is suitable for IP cores because it does not require structural information for fault simulation, dynamic compaction, or interleaved test generation....

    [...]


Journal ArticleDOI
TL;DR: A new scheme for built-in test that uses multiple-polynomial linear feedback shift registers (MP-LFSR's) and an implicit polynomial identification reduces the number of extra bits per seed to one bit is presented.
Abstract: We propose a new scheme for built-in test (BIT) that uses multiple-polynomial linear feedback shift registers (MP-LFSR's). The same MP-LFSR that generates random patterns to cover easy to test faults is loaded with seeds to generate deterministic vectors for difficult to test faults. The seeds are obtained by solving systems of linear equations involving the seed variables for the positions where the test cubes have specified values. We demonstrate that MP-LFSR's produce sequences with significantly reduced probability of linear dependence compared to single polynomial LFSR's. We present a general method to determine the probability of encoding as a function of the number of specified bits in the test cube, the length of the LFSR and the number of polynomials. Theoretical analysis and experiments show that the probability of encoding a test cube with s specified bits in an s-stage LFSR with 16 polynomials is 1-10/sup -6/. We then present the new BIT scheme that allows for an efficient encoding of the entire test set. Here the seeds are grouped according to the polynomial they use and an implicit polynomial identification reduces the number of extra bits per seed to one bit. The paper also shows methods of processing the entire test set consisting of test cubes with varied number of specified bits. Experimental results show the tradeoffs between test data storage and test application time while maintaining complete fault coverage. >

426 citations


01 Jan 1993

424 citations


"Test Data Compression Using Selecti..." refers methods in this paper

  • ...These techniques are based on LFSR reseeding [9]–[12] and combinational linear expansion networks consisting of XOR gates [13]–[15], and they have been implemented in commercial tools such as TestKompress from Mentor Graphics [1], SmartBIST from IBM/Cadence [3], and DBIST from Synopsys [16]....

    [...]


Proceedings ArticleDOI
Vivek De1, Shekhar Borkar1
17 Aug 1999
TL;DR: Key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance are discussed, with particular focus on short-channel effects, device parameter variations, excessive subthreshold and gate oxide leakage.
Abstract: We discuss key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance. In particular, we focus on short-channel effects, device parameter variations, excessive subthreshold and gate oxide leakage, as the main obstacles dictated by fundamental device physics. Functionality of special circuits in the presence of high leakage, SRAM cell stability, bit line delay scaling, and power consumption in clocks & interconnects, will be the primary design challenges in the future. Soft error rate control and power delivery pose additional challenges. All of these problems are further compounded by the rapidly escalating complexity of microprocessor designs. The excessive leakage problem is particularly severe for battery-operated, high-performance microprocessors.

338 citations


Frequently Asked Questions (1)
Q1. What are the contributions mentioned in the paper "Test data compression using selective encoding of scan slices" ?

The authors present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property ( IP ) cores. The authors present compression results for a number of industrial circuits and compare their results to other recent compression methods targeted at IP cores. In the best case, the authors can achieve compression by a factor of using only one tester clock cycle per slice.