Test of RAM-based FPGA: methodology and application to the interconnect
27 Apr 1997-pp 230-237
TL;DR: A methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices is proposed and it is demonstrated that a set of only 3 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant.
Abstract: This paper proposes a methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices. Two different approaches with different objectives are identified: the Manufacturing Test Procedure and the User Test Procedure. The proposed method is used to generate a Manufacturing Test Procedure targeting the Interconnect Structure of RAM-based FPGA. It is demonstrated that a set of only 3 Test Configurations called the Orthogonal, the Diagonal-1 and Diagonal-2 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant. Then the test of each configuration is shown equivalent to the test of classical buses. The final proposed Manufacturing Test Procedure present a constant number of Test Configurations (3) and very short Test Sequences.
Citations
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18 Oct 1998
TL;DR: The first BIST approach for testing the programmable routing network in FPGAs is introduced, which detects opens in, and shorts among, wiring segments, and also faults affecting theprogrammable switches that configure the FPGA interconnect.
Abstract: We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affecting the programmable switches that configure the FPGA interconnect. As a result, the BIST technique provides complete testing of interconnect faults.
180 citations
TL;DR: The authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.
Abstract: Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.
170 citations
Proceedings Article•
01 Jan 2001
TL;DR: This work introduces the first diagnosis method for multiple faulty PLBs; for any faulty PLB, it is introduced its internal faulty modules or modes of operation and provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems.
Abstract: We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.
127 citations
Cites background from "Test of RAM-based FPGA: methodology..."
...Interconnect testing targets faults such as shorts, opens, and programmable switches stuck-on and stuck-off....
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TL;DR: In this article, the authors present a built-in self-test (BIST) approach able to diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution.
Abstract: We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.
125 citations
TL;DR: The first online built-in self-test (BIST) and BIST-based diagnosis of programmable logic resources in field-programmable gate arrays (FPGAs) is presented.
Abstract: We present the first online built-in self-test (BIST) and BIST-based diagnosis of programmable logic resources in field-programmable gate arrays (FPGAs). These techniques were implemented and used in a roving self-testing areas (STARs) approach to testing and reconfiguration of FPGAs for fault-tolerant applications. The BIST approach provides complete testing of the programmable logic blocks (PLBs) in the FPGA during normal system operation. The BIST-based diagnosis can identify any group of faulty PLBs, then applies additional diagnostic configurations to identify the faulty look-up table or flip-flop within a faulty PLB. The ability to locate defective modules inside a PLB enables a new form of fault-tolerance that reuses partially defective PLBs in their fault-free modes of operation.
71 citations
References
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01 Jan 1994
TL;DR: The purpose of this chapter was to discuss the design and implementation of SRAM Programmable FPGAs, as well as some of the techniques used in the development of Erasable Programmable Logic Devices.
Abstract: Preface. 1: Introduction. 1.1. Logic Implementation Options. 1.2. What is an FPGA? 1.3. Advantages of FPGAs. 1.4. Disadvantages of FPGAs. 1.5. Technology Trends. 1.6. Designing for FPGAs. 1.7. Outline of Subsequent Chapters. 1.8. References. 2: SRAM Programmable FPGAs. 2.1. Introduction. 2.2. Programming Technology. 2.3. Device Architecture. 2.4. Software. 2.5. The Future. 2.6. Design Applications. 2.7. Acknowledgements 2.8. References. 3. Antifuse Programmed FPGAs. 3.1. Introduction. 3.2. Programming Technology. 3.3. Device Architecture. 3.4. Software. 3.5. The Future. 3.6. Design Applications. 3.7. Acknowledgements. 3.8. References. 4. Erasable Programmable Logic Devices. 4.1. Introduction. 4.2. Programming Technology. 4.3. Device Architecture. 4.4. Software. 4.5. The Future. 4.6. Design Applications. 4.7. References. Index.
345 citations
TL;DR: An algorithm is derived for multiprobe testing for shorts, opens, and wiring errors in any multiterminal wiring network, such as a printed circuit board, wiring harness, multiconductor cable, or backplane wiring board.
Abstract: An algorithm is derived for multiprobe testing for shorts, opens, and wiring errors in any multiterminal wiring network, such as a printed circuit board, wiring harness, multiconductor cable, or backplane wiring board. For behavioral testing the minimum number of tests required, always achievable, is equal to p - 1 + [log 2 q], where p is the number of terminals in the largest interconnected cluster in the network, and q is the total number of clusters, including isolated terminals. For structural testing the number of tests required is less, and can be as small as [log 2 q] + 1 depending upon the assumptions made regarding the types of faults that can occur.
183 citations
29 Aug 1989
TL;DR: A novel framework for analyzing test generation and diagnosis algorithms for wiring interconnect are presented, and a property of test vector sets, called diagonal independence, which guarantees the diagnostic resolution of the vector test set is identified.
Abstract: A novel framework for analyzing test generation and diagnosis algorithms for wiring interconnect are presented. A property of test vector sets, called diagonal independence, which guarantees the diagnostic resolution of the vector test set is identified. The failing responses or syndromes are classified into aliasing and confounding syndromes, and this classification permits precise analysis of the diagnostic capabilities of different test algorithms. Using this framework, all the algorithms that have been proposed for board interconnect testing are analyzed. Their capabilities and limitations are clearly defined. A new optimal adaptive algorithm that can reduce test and diagnosis complexity is also presented. >
166 citations
12 Sep 1988
TL;DR: A built-in self-test of interconnects based on boundary scan architecture is described in this paper, where detection and diagnosis schemes are proposed which provide minimal-size test vector sets.
Abstract: A built-in self-test of interconnects based on boundary scan architecture is described. Detection and diagnosis schemes are proposed which provide minimal-size test vector sets. I/O scan chains order independent test vector sets and walking sequences. Properties like ease of test vector generation, structure-independent detection and diagnosis, and local response compaction have made the developed schemes suitable for built-in-self-test implementation. An example board-interconnect test session is described using one of the proposed schemes. >
140 citations
IBM1
TL;DR: The ECIPT methodology additionally provides a mechanism for simplified tests of failures associated with interchip wiring and chip I/O connections.
Abstract: Electronic Chip-in-Place Test (ECIPT) is a design approach and a test methodology for VLSI packages containing multiple semi-conductor chips. Shift register latches are used in such a way that each chip on a package is accessible for testing from the package pins without in-circuit probing. A means is therefore provided, whereby tests generated for a chip can be reapplied at the package level. The ECIPT methodology additionally provides a mechanism for simplified tests of failures associated with interchip wiring and chip I/O connections.
109 citations