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Book ChapterDOI

Testing for Bridging Faults

TL;DR: In this article, the Bridging-Fault Model Detection of Nonfeedback Bridging Faults Detection of Feedback Bridging Fault Detection of feedback Bridging fault detection of feedback is discussed.
Abstract: This chapter contains sections titled: The Bridging-Fault Model Detection of Nonfeedback Bridging Faults Detection of Feedback Bridging Faults Bridging Faults Simulation Test Generation for Bridging Faults Concluding Remarks This chapter contains sections titled: References Problems
Citations
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Book
01 Jun 1994
TL;DR: In this paper, a general model of the switch is used to construct testing sequences for the internal functions of the f*f switch, requiring only O(f/sup 2/2/sup f/) tests in the case of round-robin priority and O (f 2/sup 1/1/1/) tests for fixed priority (f is a constant that is less than or equal to eight).
Abstract: The authors present efficient methods for testing packet-switched multistage interconnection networks. In addition to testing the data paths and routing capabilities, tests for detecting faults in the control circuitry including the conflict resolution capabilities are provided. Using a general model of the switch, testing sequences are constructed for the internal functions of the f*f switch requiring only O(f/sup 2/2/sup f/) tests in the case of round-robin priority and O(f2/sup f-1/) in the case of fixed priority (f is usually a constant that is less than or equal to eight). Algorithms are then presented to test the entire network using at most twice the number of tests needed to test a switch, independently of the network size, which results in O(log N) testing time for an N-processor network. It is shown that the method achieves higher coverage and several-orders-of-magnitude reduction in the testing time of complex multiprocessor systems compared to previous methods. >

16 citations

Journal ArticleDOI
TL;DR: The authors present efficient methods for testing packet-switched multistage interconnection networks and shows that the method achieves higher coverage and several-orders-of-magnitude reduction in the testing time of complex multiprocessor systems compared to previous methods.
Abstract: The authors present efficient methods for testing packet-switched multistage interconnection networks. In addition to testing the data paths and routing capabilities, tests for detecting faults in the control circuitry including the conflict resolution capabilities are provided. Using a general model of the switch, testing sequences are constructed for the internal functions of the f*f switch requiring only O(f/sup 2/2/sup f/) tests in the case of round-robin priority and O(f2/sup f-1/) in the case of fixed priority (f is usually a constant that is less than or equal to eight). Algorithms are then presented to test the entire network using at most twice the number of tests needed to test a switch, independently of the network size, which results in O(log N) testing time for an N-processor network. It is shown that the method achieves higher coverage and several-orders-of-magnitude reduction in the testing time of complex multiprocessor systems compared to previous methods. >

13 citations

Proceedings ArticleDOI
27 Aug 2009
TL;DR: An overview about todays challenges in interconnect technology and potential resulting physical faults is given and Arrow is a generic hardware fault injection tool, written in the hardware description language VHDL, especially designed for digital fault injection on the interconnect of NoCs, making use of fault models from the logical level.
Abstract: Todays NoCs are reaching a level where it is getting very hard to ensure 100% of functionality. Consequently, fault tolerance has become an important aspect in todays design techniques and like the system itself, it has to be validated and tested. A vulnerable point of attack for faults in distribiuted systems like NoCs is certainly the interconnect. In this paper, we will give an overview about todays challenges in interconnect technology and potential resulting physical faults. Unfortunately, describing faults on the physical level is far too accurate and so it is necessary to abstract and to map all these faults to a logical level. In more complex systems, also the logical level may become too detailed. As a result, an even more abstract layer, which is defined as the functional level, has to be introduced. To be able to verify fault tolerance, an experiment based test approach like fault injection is necessary. Arrow is a generic hardware fault injection tool, written in the hardware description language VHDL, especially designed for digital fault injection on the interconnect of NoCs, making use of fault models from the logical level. 1

4 citations


Cites background or methods from "Testing for Bridging Faults"

  • ...A FBF can potentially turn a combinatorial circuit into a sequential one [ 10 ]....

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  • ...According to [ 10 ], between 40% and 50% of all faults can be modeled with the BF model....

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  • ...Pull-up and pull-down strength depends on the used technology, transistor size and on the count of the conducting tranistors [ 10 ]....

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  • ...The MBF can simplified be seen as several SBFs with common lines [ 10 ]....

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01 Jan 2009
TL;DR: Two topics that have not been tested yet in the field of private and confessional basic education are related and opens up space for managerial implications, since it can contribute to educational managers improving their KM practices and achieving better performance in environmental processes educational.
Abstract: This thesis discusses the relationship between the processes of Knowledge Management (KM) and its impact on the performance on brazilian private and confessional basic education schools. From the theoretical point of view, it is based on the perspective of organizational analysis advocated by the Knowledge Based View (KVB). The central themes related to the work are articulated from there: Organizational Strategy, Organizational Performance, Processes and Models of KM Evaluation. With regard to organizational performance, the Balanced Scorecard (BSC) evaluation perspective was taken as the basis. In this way, the hypotheses of the thesis relate the impact of the four processes of GC Creation, Storage, Sharing and Creation in the perspectives of results of the BSC People, Internal Processes, Clients and Sustainability besides verifying the correlation between these constructs. The study is based on a positivist view of science and as a method, the multi-method approach was chosen sequentially with the development of a qualitative and a quantitative phase. In the first stage, semi-structured interviews were conducted with six school managers from Brazil and Spain to understand how the subject of KM and organizational performance in the field. With the results of the qualitative phase the quantitative phase of the research was carried out by applying a questionnaire with 50 items, from already used and validated scales, exploring the eight constructs of the hypotheses. The survey collected 242 responses, which were used for the development of the Structural Equation Modeling (SEM) technique. The proposed theoretical model was verified from the relationships and the study of paths. As a result, it was possible to verify the influence of KM processes on the BSC dimensions of educational organizations. The influence of KM processes on the organizational performance of schools has been evident, since all processes in some way impact the organizational results dimensions. It was possible to verify the role that the creation of knowledge exerts on the people in the organization, and also how the storage of knowledge impacts the perspectives of people, internal processes and sustainability. As an academic contribution, the study relate two topics that have not been tested yet in the field of private and confessional basic education and opens up space for managerial implications, since it can contribute to educational managers improving their KM practices and achieving better performance in environmental processes educational.
References
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Journal ArticleDOI
K.C.Y. Mei1
TL;DR: The commonly used stuck-at fault fails to model logic circuit shorts, so Bridging faults are defined to model these circuit mal-functions.
Abstract: The commonly used stuck-at fault fails to model logic circuit shorts. Bridging faults are defined to model these circuit mal-functions. This model is based on wired logic which is a characteristic of many logic families such as resistor-transistor logic (RTL), diode transistor logic (DTL), emitter-coupled logic (ECL), etc. It does not apply to TTL circuits. The model also limits to fan-out-free leads.

248 citations


"Testing for Bridging Faults" refers background in this paper

  • ...[ 2 ] most of the MBFs are detected by tests for component SBFs, therefore most of the work...

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  • ...lations [ 2 ] which are hard to detect by the testing equipment....

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  • ...In [ 2 ] has been shown that, for fan-out free circuits, SSF tests can detect several classes...

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Journal ArticleDOI
Abramovici1, Menon
TL;DR: This approach is based on extending fault simulation and test generation for stuck faults to cover bridging faults as well, and shows that adequate bridging fault coverage can be obtained in most cases without using sequences of vectors.
Abstract: In this correspondence we prepent a practical approach to fault simulation and test generation for bridging faults in combinational circuits. Unlike previous work, we consider Unrestricted bridging faults, including those that introduce feedback. Our approach is based on extending fault simulation and test generation for stuck faults to cover bridging faults as well. We consider combinational testing only, and show that adequate bridging fault coverage can be obtained in most cases without using sequences of vectors.

98 citations


"Testing for Bridging Faults" refers background or methods in this paper

  • ...Bridging faults (BFs) are caused by shorts between normally unconnected signal lines (Fi- gure 1.a), [ 1 ]....

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  • ...used. Most of the work done in this area uses simple wired models [ 1 ]-[3], [6]....

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  • ...then of the same order of magnitude as the number of SSFs as shown in [ 1 ]....

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  • ...set for SSFs, thus explicit enumeration of all BFs is avoided. In [ 1 ] an implicit simulation meth-...

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Journal ArticleDOI
TL;DR: It is shown that only two test patterns are sufficient to detect feedback bridging faults between input and output lines of a general combinational network.
Abstract: The testing of bridging faults (short circuits) has become increasingly important with the increasing density in VLSI (very large scale integration) chips. Yet very little work has been done in this area. In this correspondence, based on a two-state sequential machine model, we present the conditions for a circuit with feedback bridgings to oscillate and to exhibit stable sequential behavior. It is shown that only two test patterns are sufficient to detect feedback bridging faults between input and output lines of a general combinational network. We derive a simple equation to generate test patterns for detecting feedback bridging faults among internal lines of a general combinational network.

20 citations


"Testing for Bridging Faults" refers methods in this paper

  • ...Later, in [ 6 ], the authors use a two-state sequential machine model (Mealey) to conclude...

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  • ...used. Most of the work done in this area uses simple wired models [1]-[3], [ 6 ]....

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