Testing for Single Stuck Faults
01 Jan 1990-pp 181-287
TL;DR: This chapter contains sections titled: Basic Issues ATG for SSFs in Combinational Circuits ATG in Sequential Circuits Concluding Remarks.
Abstract: This chapter contains sections titled: Basic Issues ATG for SSFs in Combinational Circuits ATG for SSFs in Sequential Circuits Concluding Remarks This chapter contains sections titled: References Problems
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TL;DR: It is shown that even if t was generated using dynamic test compaction heuristics, it is possible to improve t further, and when t is partially specified to accommodate test data compression, the test vector improvement step does not change the number of unspecified bits of t.
Abstract: We investigate the introduction of a new step, referred to as test vector improvement, into test generation processes. After a fully specified test vector or a partially specified test cube t is generated at an arbitrary iteration of the test generation process, the test vector improvement step modifies t so as to increase the number of yet-undetected target faults that t detects. This is done in this paper using a simulation-based process. We show that even if t was generated using dynamic test compaction heuristics, it is possible to improve t further. When t is partially specified to accommodate test data compression, the test vector improvement step does not change the number of unspecified bits of t. The final result is a smaller test set and/or a higher fault coverage (if the test generation process does not detect all the detectable faults).
17 citations
Additional excerpts
...Index Terms—Dynamic test compaction, full-scan circuits, stuck-at faults, test cubes, test generation, transition faults....
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TL;DR: This paper describes HLFM for analog circuits using an adaptive self-tuning algorithm called multiple model generation system using delta that can handle both linear and nonlinear fault situations with better accuracy than previously published HLFMs.
Abstract: High-level modeling for operational amplifiers (opamps) has been previously carried out successfully using models generated by published automated model generation approaches. Furthermore, high-level fault modeling (HLFM) has been shown to work reasonably well using manually designed fault models. However, no evidence shows that published automated model generation approaches based on opamps have been used in HLFM. This paper describes HLFM for analog circuits using an adaptive self-tuning algorithm called multiple model generation system using delta. The generation algorithms and simulation models were written in MATLAB and the hardware description language VHDL-AMS, respectively. The properties of these self-tuning algorithms were investigated by modeling complementary metal-oxide-semiconductor opamps, and comparing simulations using the HLFM against those of the original simulation program with integrated circuit emphasis circuit utilizing transient analysis. Results show that the models can handle both linear and nonlinear fault situations with better accuracy than previously published HLFMs.
14 citations
TL;DR: It is demonstrated that undetectable single stuck-at faults in full-scan benchmark circuits tend to cluster in certain areas, which implies that certain areas may remain uncovered by a test set for single stuck -at faults.
Abstract: We demonstrate that undetectable single stuck-at faults in full-scan benchmark circuits tend to cluster in certain areas. This implies that certain areas may remain uncovered by a test set for single stuck-at faults. We describe an extension to the set of target faults aimed at providing a better coverage of the circuit in the presence of undetectable single stuck-at faults. The extended set of target faults consists of double stuck-at faults that include an undetectable fault as one of their components. The other component is a detectable fault adjacent to the undetectable fault. We present experimental results of fault simulation and test generation for the extended set of target faults.
8 citations
04 Jul 2013
TL;DR: It is found that LFSR techniqque seems to be good when compared to the ATPG tool for the small and medium circuits, which yields 100% fault coverage where as Tetramax is giving about 97% fault Coverage.
Abstract: The test generation problem for circuits is known to be NP-hard. Efficient techniques for test generation are essential in order to reduce the test generation time. Test patterns were generated using ATPG (Automatic Test Pattern Generation) and faults were inserted in the netlist file generated using DFT (Design for Test). Here ATPG is achieved using the combination of Design Compiler and the Tetramax. Fault coverage and test patterns were generated. It was observed that neither a comprehensive functional verification sequence nor a sequence with high stuck-at fault coverage gives high transition fault coverage for sequential circuits. A customized LFSR algorithm is used to find the fault coverage and pattern used to detect the faults. It is found that LFSR techniqque seems to be good when compared to the ATPG tool for the small and medium circuits. LFSR technique yields 100% fault coverage where as Tetramax is giving about 97% fault coverage.
7 citations
Cites background or methods from "Testing for Single Stuck Faults"
...PODEM was created in 1981 when shortcomings in D Algorithm became evident when design innovations resulted in circuits that D Algorithm could not realize[2]....
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...It uses a pseudorandom number generator to generate test vectors, and relies on logic simulation to compute good machine results, and fault simulation to calculate the fault coverage of the generated vectors[2]....
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...Early test generation algorithms such as Booleandifference and literal proposition were not practical to implement on a computer[2]....
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...Methods based on Boolean satisfiability are sometimes used to generate test vectors[2]....
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...Here we are inserting an multiplexer style of scan cells[2] for satisfying adhoc design rules....
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01 Apr 2019
TL;DR: It is observed that while the ATPG does not yield 100% fault coverage,NLFSR technique gives 100% coverage and the difference in on-chip power between LFSR and NLFSR is also found to be very large with NL FSR consuming more than 80% less power than L FSR.
Abstract: The generation of test patterns for the detection of faults in VLSI circuits is the most integral part of fault detection. The patterns are generated using Pseudorandom Number Generator (PRNG) and applied to the circuits. The most commonly used PRNG is Linear Feedback Shift Register (LFSR). Other than LFSR, Non-Linear Feedback Shift Registers (NLFSR) can also be used as pattern generator. This paper mainly focuses on the advantages of using NLFSRs over ATPG. It compares the fault coverage of single stuck-at faults using NLFSR technique with the fault coverage of single stuck-at faults using ATPG tool for few ISCAS’89 circuits. This paper also shows the reduction in terms of total on-chip power while using NLFSR as pattern generator instead of LFSR. The netlist generation of the circuits is done by using Synopsys Design Compiler tool and ATPG is achieved using Synopsys TetraMax tool. In the NLFSR technique, faults are injected manually and patterns are added to the CUT to get the fault coverage. The faults injected in the circuits are detected in the simulation results of the faulty circuit. The NLFSRs and LFSRs are designed using Xilinx Vivado. The comparison between the fault coverage and power consumption of the techniques are shown in a tabular form and the simulation results for NLFSR technique is shown. It is observed that while the ATPG does not yield 100% fault coverage, NLFSR technique gives 100% coverage. The difference in on-chip power between LFSR and NLFSR is also found to be very large with NLFSR consuming more than 80% less power than LFSR.
7 citations
Additional excerpts
...BIST is an approach in which integrated circuits are designed with supplemental hardware and software attributes for testing them by itself which provides economic profit [5]....
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