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The 3D Stacking Bipolar RRAM for High Density

01 Jan 2012-Vol. 11, Iss: 5, pp 945
TL;DR: In this article, two 3D stacking structures built upon bipolar RRAM crossbars are proposed to enable multilayer accesses while avoiding the overwriting induced by the cross-layer disturbance.
Abstract: For its simple structure, high density, and good scalability, the resistive random access memory (RRAM) has emerged as one of the promising candidates for large data storage in computing systems. Moreover, building up RRAM in a 3-D stacking structure further boosts its advantage in array density. Conventionally, multiple bipolar RRAM layers are piled up vertically separated with isolation material to prevent signal interference between the adjacent memory layers. The process of the isolation material increases the fabrication cost and brings in the potential reliability issue. To alleviate the situation, we introduce two novel 3-D stacking structures built upon bipolar RRAM crossbars that eliminate the isolation layers. The bigroup operation scheme dedicated for the proposed designs to enable multilayer accesses while avoiding the overwriting induced by the cross-layer disturbance is also presented. Our simulation results show that the proposed designs can increase the capacity of a memory island to 8K-bits (i.e., eight layers of 32 × 32 crossbar arrays) while maintaining the sense margin in the worst case configuration greater than 20% of the maximal sensing voltage.
Citations
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Journal ArticleDOI
TL;DR: In this article, the authors conduct a survey on several published valence change resistive switching memories with a particular interest in the I-V characteristic and the corresponding conduction mechanism.
Abstract: Resistive switching effect in transition metal oxide (TMO) based material is often associated with the valence change mechanism (VCM). Typical modeling of valence change resistive switching memory consists of three closely related phenomena, i.e., conductive filament (CF) geometry evolution, conduction mechanism and temperature dynamic evolution. It is widely agreed that the electrochemical reduction-oxidation (redox) process and oxygen vacancies migration plays an essential role in the CF forming and rupture process. However, the conduction mechanism of resistive switching memory varies considerably depending on the material used in the dielectric layer and selection of electrodes. Among the popular observations are the Poole-Frenkel emission, Schottky emission, space-charge-limited conduction (SCLC), trap-assisted tunneling (TAT) and hopping conduction. In this article, we will conduct a survey on several published valence change resistive switching memories with a particular interest in the I-V characteristic and the corresponding conduction mechanism.

474 citations

Journal ArticleDOI
TL;DR: In this article, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit, and an optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation.
Abstract: The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I-V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation.

155 citations

Journal ArticleDOI
TL;DR: A Memristor-based dynamic (MD) synapse design with experiment-calibrated memristor models is proposed and a temporal pattern learning application was investigated to evaluate the use of MD synapses in spiking neural networks, under both spike-timing-dependent plasticity and remote supervised method learning rules.
Abstract: Recent advances in memristor technology lead to the feasibility of large-scale neuromorphic systems by leveraging the similarity between memristor devices and synapses For instance, memristor cross-point arrays can realize dense synapse network among hundreds of neuron circuits, which is not affordable for traditional implementations However, little progress was made in synapse designs that support both static and dynamic synaptic properties In addition, many neuron circuits require signals in specific pulse shape, limiting the scale of system implementation Last but not least, a bottom-up study starting from realistic memristor devices is still missing in the current research of memristor-based neuromorphic systems Here, we propose a memristor-based dynamic (MD) synapse design with experiment-calibrated memristor models The structure obtains both static and dynamic synaptic properties by using one memristor for weight storage and the other as a selector We overcame the device nonlinearities and demonstrated spike-timing-based recall, weight tunability, and spike-timing-based learning functions on MD synapse Furthermore, a temporal pattern learning application was investigated to evaluate the use of MD synapses in spiking neural networks, under both spike-timing-dependent plasticity and remote supervised method learning rules

83 citations

Journal ArticleDOI
TL;DR: This paper proposes a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, local information processing is achieved in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross- point selector devices.
Abstract: The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations, has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder and sum-of-products logic functions. We compare certain features of the proposed logic-in-memory approach with another work of the literature, and present an analysis of circuit resources, integration density, and logic computation parallelism.

59 citations

Journal ArticleDOI
TL;DR: Analysis of the row grounding technique shows that increasing the number of rows can help reduce read latency and energy, in contrast to the case of capacitive memory arrays.
Abstract: Summary Using memristive devices within a crossbar array could pave the way for memories with higher density and speed than state-of-the-art Flash memory, while maintaining relatively low energy. However, memristive crossbar arrays have great difficulty distinguishing logical states because of sneak path currents. The row grounding technique eliminates the sneak path effect, allowing reliable sampling of the memristor state. In this paper, we analyze the row grounding technique and propose several methods and constraints for the design of memristive crossbar arrays. When the row grounding technique is used for these arrays, our analysis shows that increasing the number of rows can help reduce read latency and energy, in contrast to the case of capacitive memory arrays. Simulation results confirm the theoretical analysis proposed in this paper. Copyright © 2017 John Wiley & Sons, Ltd.

28 citations

References
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Journal ArticleDOI
TL;DR: In this article, the memristor is introduced as the fourth basic circuit element and an electromagnetic field interpretation of this relationship in terms of a quasi-static expansion of Maxwell's equations is presented.
Abstract: A new two-terminal circuit element-called the memristorcharacterized by a relationship between the charge q(t)\equiv \int_{-\infty}^{t} i(\tau) d \tau and the flux-linkage \varphi(t)\equiv \int_{- \infty}^{t} v(\tau) d \tau is introduced as the fourth basic circuit element. An electromagnetic field interpretation of this relationship in terms of a quasi-static expansion of Maxwell's equations is presented. Many circuit-theoretic properties of memistors are derived. It is shown that this element exhibits some peculiar behavior different from that exhibited by resistors, inductors, or capacitors. These properties lead to a number of unique applications which cannot be realized with RLC networks alone. Although a physical memristor device without internal power supply has not yet been discovered, operational laboratory models have been built with the help of active circuits. Experimental results are presented to demonstrate the properties and potential applications of memristors.

7,585 citations

Journal ArticleDOI
TL;DR: A coarse-grained classification into primarily thermal, electrical or ion-migration-induced switching mechanisms into metal-insulator-metal systems, and a brief look into molecular switching systems is taken.
Abstract: Many metal–insulator–metal systems show electrically induced resistive switching effects and have therefore been proposed as the basis for future non-volatile memories. They combine the advantages of Flash and DRAM (dynamic random access memories) while avoiding their drawbacks, and they might be highly scalable. Here we propose a coarse-grained classification into primarily thermal, electrical or ion-migration-induced switching mechanisms. The ion-migration effects are coupled to redox processes which cause the change in resistance. They are subdivided into cation-migration cells, based on the electrochemical growth and dissolution of metallic filaments, and anion-migration cells, typically realized with transition metal oxides as the insulator, in which electronically conducting paths of sub-oxides are formed and removed by local redox processes. From this insight, we take a brief look into molecular switching systems. Finally, we discuss chip architecture and scaling issues.

4,547 citations

Journal ArticleDOI
TL;DR: The memristor is a 2-terminal nonvolatile memory device that exhibits a pinched hysteresis loop confined to the first and third quadrants of the v-i plane whose contour shape in general changes with both the amplitude and frequency of any periodic sine-wave-like input voltage source, or current source as mentioned in this paper.
Abstract: All 2-terminal non-volatile memory devices based on resistance switching are memristors, regardless of the device material and physical operating mechanisms. They all exhibit a distinctive “fingerprint” characterized by a pinched hysteresis loop confined to the first and the third quadrants of the v–i plane whose contour shape in general changes with both the amplitude and frequency of any periodic “sine-wave-like” input voltage source, or current source. In particular, the pinched hysteresis loop shrinks and tends to a straight line as frequency increases. Though numerous examples of voltage vs. current pinched hysteresis loops have been published in many unrelated fields, such as biology, chemistry, physics, etc., and observed from many unrelated phenomena, such as gas discharge arcs, mercury lamps, power conversion devices, earthquake conductance variations, etc., we restrict our examples in this tutorial to solid-state and/or nano devices where copious examples of published pinched hysteresis loops abound. In particular, we sampled arbitrarily, one example from each year between the years 2000 and 2010, to demonstrate that the memristor is a device that does not depend on any particular material, or physical mechanism. For example, we have shown that spin-transfer magnetic tunnel junctions are examples of memristors. We have also demonstrated that both bipolar and unipolar resistance switching devices are memristors.

1,208 citations

Journal ArticleDOI
TL;DR: A complementary resistive switch is introduced that consists of two antiserial memristive elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption.
Abstract: On the road towards higher memory density and computer performance, a significant improvement in energy efficiency constitutes the dominant goal in future information technology. Passive crossbar arrays of memristive elements were suggested a decade ago as non-volatile random access memories (RAM) and can also be used for reconfigurable logic circuits. As such they represent an interesting alternative to the conventional von Neumann based computer chip architectures. Crossbar architectures hold the promise of a significant reduction in energy consumption because of their ultimate scaling potential and because they allow for a local fusion of logic and memory, thus avoiding energy consumption by data transfer on the chip. However, the expected paradigm change has not yet taken place because the general problem of selecting a designated cell within a passive crossbar array without interference from sneak-path currents through neighbouring cells has not yet been solved satisfactorily. Here we introduce a complementary resistive switch. It consists of two antiserial memristive elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption.

1,170 citations

01 Jan 2019
TL;DR: The goal of this tutorial is to introduce some fundamental circuit-theoretic concepts and properties of the memristor that are relevant to the analysis and design of non-volatile nano memories where binary bits are stored as resistances manifested by the Memristor’s continuum of equilibrium states.
Abstract: All 2-terminal non-volatile memory devices based on resistance switching are memristors, regardless of the device material and physical operating mechanisms. They all exhibit a distinctive “fingerprint” characterized by a pinched hysteresis loop confined to the first and the third quadrants of the v–i plane whose contour shape in general changes with both the amplitude and frequency of any periodic “sine-wave-like” input voltage source, or current source. In particular, the pinched hysteresis loop shrinks and tends to a straight line as frequency increases. Though numerous examples of voltage vs. current pinched hysteresis loops have been published in many unrelated fields, such as biology, chemistry, physics, etc., and observed from many unrelated phenomena, such as gas discharge arcs, mercury lamps, power conversion devices, earthquake conductance variations, etc., we restrict our examples in this tutorial to solid-state and/or nano devices where copious examples of published pinched hysteresis loops abound. In particular, we sampled arbitrarily, one example from each year between the years 2000 and 2010, to demonstrate that the memristor is a device that does not depend on any particular material, or physical mechanism. For example, we have shown that spin-transfer magnetic tunnel junctions are examples of memristors. We have also demonstrated that both bipolar and unipolar resistance switching devices are memristors.

1,097 citations