The DAC 2012 routability-driven placement contest and benchmark suite
IBM1
03 Jun 2012-pp 774-782
TL;DR: The aim of the DAC 2012 routability-driven placement contest is to release challenging benchmark designs that are derived from modern industrial ASICs, and contain information to perform both placement and routing, and present a new congestion metric, as well as an accurate congestion analysis framework to evaluate and compare the routability of various placement algorithms.
Abstract: Existing routability-driven placers mostly employ rudimentary and often crude congestion models that fail to account for the complexities in modern designs, e.g., the impact of non-uniform wiring stacks, layer directives, partial and/or complete routing blockages, etc. In addition, they are hampered by congestion metrics that do not accurately score or represent design congestion. This is in large part due to the non-availability of public designs depicting industrial wiring stacks and other complexities affecting design routability. The aim of the DAC 2012 routability-driven placement contest is to address these issues, by way of the following: (a) release challenging benchmark designs that are derived from modern industrial ASICs, and contain information to perform both placement and routing, (b) present a new congestion metric, as well as an accurate congestion analysis framework to evaluate and compare the routability of various placement algorithms. We hope that a set of challenging benchmarks, along with a standard, publicly available evaluation framework will further advance research in routability-driven placement.
Citations
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29 Mar 2015
TL;DR: The ISPD~2015 placement-contest benchmarks include all the detailed pin, cell, and wire geometry constraints from the 2014 release, plus added fence regions and placement blockages and specified upper limits on local cell-area density.
Abstract: The ISPD~2015 placement-contest benchmarks include all the detailed pin, cell, and wire geometry constraints from the 2014 release, plus(a) added fence regions and placement blockages,(b) altered netlists including fixed macro blocks,(c) reduced standard cell area utilization via larger floorplan outlines, and(d)] specified upper limits on local cell-area density.Compared to the 2014 release, these new constraints add realism and increase the difficulty of producing detail-routable wirelength-driven placements.
114 citations
Cites methods from "The DAC 2012 routability-driven pla..."
...…Descriptors B.7.2 [Integrated Circuits]: Design Aids - Placement and Routing; D.2.8 [Software Engineering]: Metrics—complexity measures, performance measures General Terms Algorithms, Design Keywords Placement; routability; placement evaluation; global routing; detailed routing; fence regions...
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...We attribute these results to the use of a wirelength objective coupled with fine-grain design-constraint-aware look-ahead legalization....
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TL;DR: RePlAce is the first work to achieve superior solution quality across all the IS PD-2005, ISPD-2006, MMS, DAC-2012, and ICCAD-2012 benchmark suites with a single global placement engine.
Abstract: The Nesterov’s method approach to analytic placement has recently demonstrated strong solution quality and scalability. We dissect the previous implementation strategy and show that solution quality can be significantly improved using two levers: 1) constraint-oriented local smoothing and 2) dynamic step size adaptation. We propose a new density function that comprehends local overflow of area resources; this enables a constraint-oriented local smoothing at per-bin granularity. Our improved dynamic step size adaptation automatically determines step size and effectively allocates optimization effort to significantly improve solution quality without undue runtime impact. Our resulting global placement tool, RePlAce, achieves an average of 2.00% half-perimeter wirelength (HPWL) reduction over all best known ISPD-2005 and ISPD-2006 benchmark results, and an average of 2.73% over all best known modern mixed-size (MMS) benchmark results, without any benchmark-specific code or tuning. We further extend our global placer to address routability, and achieve on average 8.50%–9.59% scaled HPWL reduction over previous leading academic placers for the DAC-2012 and ICCAD-2012 benchmark suites. To our knowledge, RePlAce is the first work to achieve superior solution quality across all the ISPD-2005, ISPD-2006, MMS, DAC-2012, and ICCAD-2012 benchmark suites with a single global placement engine.
100 citations
Cites background or methods from "The DAC 2012 routability-driven pla..."
..., for SUPERBLUE12 [39] ePlace routing hotspots demand 211....
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...In RePlAce, we add optimization of routability in global routing to the Nesterov’s approach, achieving substantial scaled HPWL (sHPWL) improvements over previous leading academic placers for the DAC-2012 [39] and ICCAD-2012 [40] benchmark suites....
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...Among all published results for these two benchmark suites, [7], [10], [13], [23] show leading-edge solution qualities in terms of sHPWL, considering routing congestion (RC) as a penalty factor to HPWL as defined in [39] and [40]....
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...As described in [39], the global router reports cross-tile routing segments, so that tile edge-based routing usage (#tracks used) can be obtained....
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...Experiments are performed on three types of well-studied academic benchmarks: 1) ISPD2005 [32] and ISPD-2006 [33] benchmark suites for standard cell placement; 2) the large-scale MMS [43] benchmark suite for mixed-size placement; and 3) DAC-2012 [39] and ICCAD-2012 [40] benchmark suites for global routabilitydriven placement....
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05 Nov 2012
TL;DR: The history of placement research, the progress leading up to the state of the art, and outstanding challenges are surveyed.
Abstract: Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools. We survey the history of placement research, the progress achieved up to now, and outstanding challenges.
88 citations
Cites background from "The DAC 2012 routability-driven pla..."
...The DAC 2012 Contest Benchmarks [156] were easier to route and emphasized di.erent sources of congestion....
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...The DAC 2012 Contest Benchmarks [156] were easier to route and emphasized different sources of congestion....
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TL;DR: A novel GPU-accelerated placement framework DREAMPlace is proposed, by casting the analytical placement problem equivalently to training a neural network, to achieve speedup in global placement without quality degradation compared to the state-of-the-art multithreaded placer RePlAce.
Abstract: Placement for very large-scale integrated (VLSI) circuits is one of the most important steps for design closure We propose a novel GPU-accelerated placement framework DREAMPlace, by casting the analytical placement problem equivalently to training a neural network Implemented on top of a widely adopted deep learning toolkit PyTorch , with customized key kernels for wirelength and density computations, DREAMPlace can achieve around $40\times $ speedup in global placement without quality degradation compared to the state-of-the-art multithreaded placer RePlAce We believe this work shall open up new directions for revisiting classical EDA problems with advancements in AI hardware and software
87 citations
25 Mar 2012
TL;DR: A new multilevel framework for large-scale placement called MAPLE is proposed that respects utilization constraints, handles movable macros and guides the transition between global and detailed placement.
Abstract: We propose a new multilevel framework for large-scale placement called MAPLE that respects utilization constraints, handles movable macros and guides the transition between global and detailed placement. In this framework, optimization is adaptive to current placement conditions through a new density metric. As a baseline, we leverage a recently developed at quadratic optimization that is comparable to prior multilevel frameworks in quality and runtime. A novel component called Progressive Local Refinement (ProLR) helps mitigate disruptions in wirelength that we observed in leading placers. Our placer MAPLE outperforms published empirical results --- RQL, SimPL, mPL6, NTUPlace3, FastPlace3, Kraftwerk and APlace3 -- across the ISPD 2005 and ISPD 2006 benchmarks, in terms of official metrics of the respective contests.
77 citations
Cites background from "The DAC 2012 routability-driven pla..."
...…Arbor, MI 48109 IBM Corporation, Austin, TX 78758 / §IBM Corporation, Hopewell Junction, NY 12533 mckima@umich.edu, {nviswan, alpert}@us.ibm.com, imarkov@umich.edu, ramji@us.ibm.com ABSTRACT We propose a new multilevel framework for large-scale placement called MAPLE that respects utilization…...
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References
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IBM1
TL;DR: A new benchmark suit is being released in conjunction with the ISPD2005 placement contest, directly derived from industrial ASIC designs, with circuit sizes ranging from 210 thousand to 2.1 million placeable objects.
Abstract: Without the MCNC and ISPD98 benchmarks, it would arguably not have been possible for the academic community to make consistent advances in physical design over the last decade. While still being used extensively in placement and floorplanning research, those benchmarks can no longer be considered representative of today's (and tomorrow's) physical design challenges. In order to drive physical design research over the next few years, a new benchmark suit is being released in conjunction with the ISPD2005 placement contest. These benchmarks are directly derived from industrial ASIC designs, with circuit sizes ranging from 210 thousand to 2.1 million placeable objects. Unlike the ISPD98 benchmarks, the physical structure of these designs is completely preserved, giving realistic challenging designs for today's placement tools. Hopefully, these benchmarks will help accelerate new physical design research in the placement, floor-planning, and routing.
149 citations
07 Apr 2002
TL;DR: A fast but reliable way to detect routing criticalities in VLSI chips by using a congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm.
Abstract: We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a post-placement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1,300,000 cells are presented: The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average.
134 citations
"The DAC 2012 routability-driven pla..." refers methods in this paper
...…benchmark designs that are derived from modern industrial ASICs, and contain information to perform both placement and routing, (b) present a new congestion metric, as well as an accurate congestion analysis framework to evaluate and compare the routability of various placement algorithms....
[...]
19 Jan 2009
TL;DR: This paper presents a global router that addresses the via number optimization problem throughout the entire global routing flow, and introduces the via aware Steiner tree generation, 3-bend routing and layer assignment with careful ordering to reduce via count.
Abstract: The number of vias generated during the global routing stage is a critical factor for the yield of final circuits. However, most global routers only approach the problem by charging a cost for vias in the maze routing cost function. In this paper, we present a global router that addresses the via number optimization problem throughout the entire global routing flow. We introduce the via aware Steiner tree generation, 3-bend routing and layer assignment with careful ordering to reduce via count. We integrate these three techniques into FastRoute 3.0 and achieve significant reduction in both via count and runtime.
130 citations
10 Nov 2008
TL;DR: A fast and stable global router called NTHU-Route 2.0 is presented that improves the solution quality and runtime of a state-of-the-art router by the following enhancements: a new history based cost function, new ordering methods for congested region identification and rip-up and reroute, and two implementation techniques.
Abstract: We present in this paper a fast and stable global router called NTHU-Route 2.0 that improves the solution quality and runtime of a state-of-the-art router, NTHU-Route, by the following enhancements: (1) a new history based cost function, (2) new ordering methods for congested region identification and rip-up and reroute, and (3) two implementation techniques. The experimental results show that NTHU-Router 2.0 solves all ISPD98 benchmarks with very good quality. Moreover, it routes 7 of 8 ISPD07 benchmarks without any overflow. In particular, for one of the ISPD07 benchmarks which are thought to be difficult cases previously, NTHU-Route 2.0 can completely eliminate its total overflow. NTHU-Route 2.0 also successfully solves 12 of 16 ISPD08 benchmarks without causing any overflow.
119 citations
IBM1
TL;DR: The ISPD-2011 routability-driven placement contest and the associated benchmark suite are described, and a new benchmark suite that is being released in conjunction with the contest is described, which can be used to perform both placement and global routing.
Abstract: The last few years have seen significant advances in the quality of placement algorithms. This is in part due to the availability of large, challenging testcases by way of the ISPD-2005 [17] and ISPD-2006 [16] placement contests. These contests primarily evaluated the placers based on the half-perimeter wire length metric. Although wire length is an important metric, it still does not address a fundamental requirement for placement algorithms, namely, the ability to produce routable placements.This paper describes the ISPD-2011 routability-driven placement contest, and a new benchmark suite that is being released in conjunction with the contest. All designs in the new benchmark suite are derived from industrial ASIC designs, and can be used to perform both placement and global routing. By way of the contest and the associated benchmark suite, we hope to provide a standard, publicly available framework to help advance research in the area of routability-driven placement.
106 citations