The design of high speed UART
11 Apr 2013-pp 388-390
TL;DR: The design and reliability of the Verilog HDL implementation of UART is verified by simulated waveforms, and Baud rate of 20Mbps using clock of 20MHz is used.
Abstract: Universal asynchronous receiver transmitter, abbreviated UART is a integrated circuit used for serial communications over a computer or peripheral device serial port. UARTs are now commonly included in microcontrollers. The universal designation indicates that the data format and transmission speeds are configurable and that the actual electric signaling levels and methods (such as differential signaling etc.) typically are handled by a special driver circuit external to the UART. Baud rate of 20Mbps using clock of 20MHz is used. FIFO (First-In-First Out) is used to store data temporarily during high speed transmission to get synchronization. The design is synthesized in Verilog HDL and reliability of the Verilog HDL implementation of UART is verified by simulated waveforms. We are using Cadence tool for simulation and synthesis.
Citations
More filters
01 Nov 2016
TL;DR: Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.
Abstract: A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost. Full Text: PDF
59 citations
01 Aug 2016
TL;DR: In this paper, the authors presented a feasible resolution for Rijindael's encryption and decryption using VHDL for FPGA (cyclone III) & C running over Nios II processor.
Abstract: One of the major problems in communication is the secure transportation of data over communication protocols. This paper presents a feasible resolution for Rijindael's encryption and decryption using VHDL for FPGA (cyclone III) & ‘C’ running over Nios II processor. The Nios II is a versatile embedded processor which is high performance, of lower cost and power consumption, has low complexity combining several functions into one FPGA. This paper shows implementation of AES algorithm for 128 bit data and 128 bit key in RTL (VHDL) and its software implementation using C. To measure performance in same system that is same hardware Nios II soft core processor is used. Hence this paper shows application of Advance Encryption Standard (AES) algorithm in UART for secure transfer of data in software and hardware platforms which are (RTL)VHDL and ‘C’ and further to decide suitability of its implementation of specific platform(software or hardware) depending on different baud rates supported by UART. The results are compared with the help of tools modelsim (Quartus II) and Nios II 10.1 software build tools for eclipse.
16 citations
Cites background from "The design of high speed UART"
...The UART is an integrated circuit which handles the conversion between serial and parallel data [2-4]....
[...]
04 Jul 2013
TL;DR: This paper represents designing and implementation of a Universal Asynchronous Receiver Transmitter (UART) with self-testing ability, designed with Verilog HDL language and synthesized on Spartan2 FPGA.
Abstract: With the rapid growth of Integrated Circuits (ICs) technology, the complexity of the circuits has also increased. As a result, the complexity of the circuit demands self-testability in hardware to mitigate the product failure. Built-in-self-test (BIST) is such a technique which can meet the demand of self-testability with an effective solution over costly circuit testing system. This paper represents designing and implementation of a Universal Asynchronous Receiver Transmitter (UART) with self-testing ability. In order to attain compact, stable and reliable data transmission, the UART is designed with Verilog HDL language and synthesized on Spartan2 FPGA. Here, the Baud Rate of the UART is 4 Mbps. This UART also utilizes the RS-422 standard.
13 citations
14 Nov 2014
TL;DR: This work is going to design thermal aware energy efficient Universal Asynchronous Receiver Transmitter (UART) that will create an avenue for thermal aware green communication.
Abstract: Green communication is the latest research trend practiced by researcher in green computing and network communication. There is no extensive work in green network design and no work in thermal aware network equipment design. In order to fill this research gap, we are going to design thermal aware energy efficient Universal Asynchronous Receiver Transmitter (UART) that will create an avenue for thermal aware green communication. We had achieved 59.32% to 72.96% reduction when temperature varies from 15°C to 75°C and airflow is 250 Linear Feet Per Minute (LFM), and reduction is in range of 59.30% to 72.97%, when temperature varies from 15°C to 75°C and airflow is 500 LFM. This design is implemented on Virtex 6 Field programmable Gate Array (FPGA) using Verilog.
13 citations
Additional excerpts
...There is research gap in UART design....
[...]
01 Feb 2020
TL;DR: A universal asynchronous receiver and transmitter (UART) are described, which is basically a serial data transmission protocol used in digital circuit applications that is verified using simulated waveform and synthesized on the FPGA Zed board.
Abstract: In this paper, a universal asynchronous receiver and transmitter (UART) are described, which is basically a serial data transmission protocol used in digital circuit applications. The architecture of the UART transmitter has a baud rate generator, parity generator, transmitter finite state machine (FSM) and parallel in serial out register (PISO). UART receiver has a baud rate generator, negative edge detector, parity checker, receiver finite state machine (FSM) and serial in parallel out (SIPO) register. The baud rate generator of both transmitter and receiver is the same, so the baud rate of transmitter/receiver is the same. Baud rate generator is the same as the frequency divider circuit. The data frame of the UART transmitter is 1 start bit, 8 transmits data bits, 1 parity bit and 1 stop bit. The baud rate of the transmitter and receiver is 4 Mbps using the system clock of 64 MHz’s. Implementation, simulation, and synthesis is done Xilinx Vivado 2016.2 version tool. The design is verified using simulated waveform and synthesized on the FPGA Zed board.
9 citations
Additional excerpts
...peripherals and high-speed peripheral devices [2]....
[...]
References
More filters
Book•
01 Feb 1996TL;DR: In this paper, the authors present an overview of the design of Verilog HDLs and its application in computer aided digital design (CADD), including the following: 1. Hierarchical Modeling Concepts.
Abstract: PART I. BASIC VERILOG TOPICS. 1. Overview of Digital Design with Verilog HDL. Evolution of Computer Aided Digital Design. Emergence of HDLs. Typical Design Flow. Importance of HDLs. Popularity of Verilog HDL. Trends in HDLs. 2. Hierarchical Modeling Concepts. Design Methodologies. 4-bit Ripple Carry Counter. Modules. Instances. Components of a Simulation. Example. Design Block. Stimulus Block. Summary. Exercises. 3. Basic Concepts. Lexical Conventions. Whitespace. Comments. Operators. Number Specification. Sized numbers. Unsized numbers. X or Z values. Negative numbers. Underscore characters and question marks. Strings. Identifiers and Keywords. Escaped Identifiers. Data Types. Value Set. Nets. Registers. Vectors. Integer , Real, and Time Register Data Types. Integer. Real Time. Arrays. Memories. Parameters. Strings. System Tasks and Compiler Directives. System Tasks. Displaying information. Monitoring information. Stopping and finishing in a simulation. Compiler Directives. 'define. 'include. Summary. Exercises. 4. Modules and Ports. Modules. Ports. List of Ports. Port Declaration. Port Connection Rules. Inputs. Outputs. Inouts. Width matching. Unconnected ports. Example of illegal port connection. Connecting Ports to External Signals. Connecting by ordered list. Connecting ports by name. Hierarchical Names. Summary. Exercises. 5. Gate-Level Modeling. Gate Types. And/Or Gates. Buf/Not Gates. Bufif/notif. Examples. Gate-level multiplexer. 4-bit full adder. Gate Delays. Rise, Fall, and Turn-off Delays. Rise delay. Fall delay. Turn-off delay. Min/Typ/Max Values. Min value. Typ val. Max value. Delay Example. Summary. Exercises. 6. Dataflow Modeling. Continuous Assignments. Implicit Continuous Assignment. Delays. Regular Assignment Delay. Implicit Continuous Assignment Delay. Net Declaration Delay. Expressions, Operators, and Operands. Expressions. Operands. Operators. Operator Types. Arithmetic Operators. Binary operators. Unary operators. Logical Operators. Relational Operators. Equality Operators. Bitwise Operators. Reduction Operators. Shift Operators. Concatenation Operator. Replication Operator. Conditional Operator. Operator Precedence. Examples. 4-to-1 Multiplexer. Method 1: logic equation. Method 2: conditional operator. 4-bit Full Adder. Method 1: dataflow operators. Method 2: full adder with carry lookahead. Ripple Counter. Summary. Exercises. 7. Behavioral Modeling. Structured Procedures. Initial Statement. Always Statement. Procedural Assignments. Blocking assignments. Nonblocking Assignments. Application of nonblocking assignments. Timing Controls. Delay-Based Timing Control. Regular delay control. Intra-assignment delay control. Zero delay control. Event-Based Timing Control. Regular event control. Named event control. Event OR control. Level-Sensitive Timing Control. Conditional Statements. Multiway Branching. Case Statement. Casex, casez Keywords. Loops. While Loop. For Loop. Repeat Loop. Forever loop. Sequential and Parallel Blocks. Block Types. Sequential blocks. Parallel blocks. Special Features of Blocks. Nested blocks. Named blocks. Disabling named blocks. Examples. 4-to-1 Multiplexer. 4-bit Counter. Traffic Signal Controller. Specification. Stimulus. Summary. Exercises. 8. Tasks and Functions. Differences Between Tasks and Functions. Tasks. Task Declaration and Invocation. Task Examples. Use of Input and Output Arguments. Asymmetric Sequence Generator. Functions. Function Declaration and Invocation. Function Examples. Parity calculation. Left/right shifter. Summary. Exercises. 9. Useful Modeling Techniques. Procedural Continuous Assignments. Assign and deassign. Force and release. Force and release on registers. Force and release on nets. Overriding Parameters. Defparam Statement. Module_Instance Parameter Values. Conditional Compilation and Execution. Conditional Compilation. Conditional Execution. Time Scales. Useful System Tasks. File Output. Opening a file. Writing to files. Closing files. Displaying Hierarchy. Strobing. Random Number Generation. Initializing Memory from File. Value Change Dump File. Summary. Exercises. PART II. ADVANCED VERILOG TOPICS. 10. Timing and Delays. Types of Delay Models. Distributed Delay. Lumped Delay. Pin-to-Pin Delays. Path Delay Modeling. Specify Blocks. Inside Specify Blocks. Parallel Connection. Full Connection. Specparam Statements. Conditional Path Delays. Rise, fall, and turn-off delays. Min, max, and typical delays. Handling x transitions. Timing Checks. $setup and $hold checks. $setup task. $hold task. $width Check. Delay Back-Annotation. Summary. Exercises. 11. Switch-Level Modeling. Switch-Modeling Elements. MOS Switches. CMOS Switches. Directional Switches. Power and Ground. Resistive Switches. Delay Specification on Switches. MOS and CMOS switches. Bidirectional pass switches. Specify blocks. Examples. CMOS Nor Gate. 2-to-1 Multiplexer. Simple CMOS Flip-Flop. Summary. Exercises. 12. User-Defined Primitives. UDP Basics. Parts of UDP Definition. UDP Rules. Combinational UDPs. Combinational UDP Definition. State Table Entries. Shorthand Notation for Don't Cares. Instantiating UDP Primitives. Example of a Combinational UDP. Sequential UDPs. Level-Sensitive Sequential UDPs. Edge-Sensitive Sequential UDPs. Example of a Sequential UDP. UDP Table Shorthand Symbols. Guidelines for UDP Design. Summary. Exercises. 13. Programming Language Interface. Uses of PLI. Linking and Invocation of PLI Tasks. Linking PLI Tasks. Linking PLI in Verilog-XL. Linking in VCS. Invoking PLI Tasks. General Flow of PLI Task Addition and Invocation. Internal Data Representation. PLI Library Routines. Access Routines. Mechanics of Access Routines. Types of Access Routines. Examples of Access Routines. Utility Routines. Mechanics of Utility Routines. Types of Utility Routines. Example of Utility Routines. Summary. Exercises. 14. Logic Synthesis with Verilog HDL. What Is Logic Synthesis? Impact of Logic Synthesis. Verilog HDL Synthesis. Verilog Constructs. Verilog Operators. Interpretation of a Few Verilog Constructs. The Assign statement. The if-else statement. The case statement for loops. The Function Statement. Synthesis Design Flow. RTL to Gates. RTL Description. Translation. Unoptimized Intermediate Representation. Logic Optimization. Technology Mapping and Optimization. Technology library. Design constraints. Optimized gate-level description. An Example of RTL-to-Gates. Design Sspecification. RTL description. Technology library. Design constraints. Logic synthesis. Final, Optimized, Gate-Level Description. IC Fabrication. Verification of Gate-Level Netlist. Functional Verification. Timing Verification. Modeling Tips for Logic Synthesis. Verilog Coding Style. Use meaningful names for signals and variables. Avoid mixing positive and negative edge-triggered flip-flops. Use basic building blocks vs. Use continuous assign statements. Instantiate multiplexers vs. Use if-else or case statements. Use parentheses to optimize logic structure. Use arithmetic operators *, /, and % vs. Design building blocks. Be careful with multiple assignments to the same variable. Define if-else or case statements explicitly. Design Partitioning. Horizontal partitioning. Vertical Partitioning. Parallelizing design structure. Design Constraint Specification. Example of Sequential Circuit Synthesis. Design Specification. Circuit Requirements. Finite State Machine (FSM). Verilog Description. Technology Library. Design Constraints. Logic Synthesis. Optimized Gate-Level Netlist. Verification. Summary. Exercises. PART III: APPENDICES. A. Strength Modeling and Advanced Net Definitions. B. List of PLI Routines. C. List of Keywords, System Tasks, and Compiler Directives. D. Formal Syntax Definition. E. Verilog Tidbits. F. Verilog Examples. Index.
432 citations
Book•
31 Jan 2010TL;DR: This book builds on the student's background from a first course in logic design and focuses on developing, verifying, and synthesizing designs of digital circuits.
Abstract: Advanced Digital Design with the Verilog HDL, 2e, is ideal for an advanced course in digital design for seniors and first-year graduate students in electrical engineering, computer engineering, and computer science. This book builds on the student's background from a first course in logic design and focuses on developing, verifying, and synthesizing designs of digital circuits. The Verilog language is introduced in an integrated, but selective manner, only as needed to support design examples (includes appendices for additional language details). It addresses the design of several important circuits used in computer systems, digital signal processing, image processing, and other applications.
173 citations
Book•
01 Dec 1993
TL;DR: This book explores modern digital and data communications systems, microwave radiocommunications systems, satellite communications systems), and optical fiber communications systems.
Abstract: From the Publisher:
The book explores modern digital and data communications systems, microwave radio communications systems, satellite communications systems, and optical fiber communications systems. It provides numerous examples throughout. It also includes Digital Amplitude Modulation and Frequency Shifts Keying; Signal Power in Binary Digital Signals; Digital Biphase and Statistical Time-Division Multiplexing; it updates coverage of Data Communications e.g., serial interfaces, bar codes, echoplex, checksums, RS-232D and RS-530 interface standards, Centronics parallel interface, IEEE 488 Bus, telephone network, telephone circuit, telephone circuit transmission parameters, modem control - AT command set, and CCITT modem recommendations.
31 citations
"The design of high speed UART" refers methods in this paper
...Roth, Jr, Digital System Design by using VHDL, PWS Publishing Company, 1998 [2]Samir Palintkar, Verilog HDL A Guide to Digital Design and Synthesis, Second Edition, Pearson Publication, 2011 [3] Tomasi, Wayne, Advanced electronic communication systems, Third Edition, Prentice-Hall, United States of America, 1994 [4] Michael D....
[...]