The Effects of Interconnections on High-Speed Logic Circuits
TL;DR: It is shown that high-speed circuitry must be miniaturized and the implications are discussed.
Abstract: By way of worked examples in typical but somewhat idealized cases the effect on circuit speed of circuit interconnections is studied. The source, calculation and minimization of interconnection crosstalk is also discussed. It is shown that high-speed circuitry must be miniaturized and the implications are discussed.
Citations
More filters
TL;DR: In this paper, the order of signal wires in global signal busses is continuously re-arranged to move attackers and victims away from each other, which significantly reduces the inductive coupling for the most vulnerable wires neighboring the attacker with zero area and routing resource penalty.
Abstract: Recent advances in Deep Submicron (DSM) design and manufacturing technologies have brought to the forefront the importance of inductive coupling amongst long interconnect in high performance microprocessors. Inductive coupling has been shown to depend directly on the overlap length between adjacent signal wires, the activity on these wires and the distance separating them. This paper presents a technique--known as swizzling--that exploits the inductive coupling dependence on distance to reduce the effect of any particular attacker on any of its victims. In the swizzling technique, the order of signal wires in global signal busses is continuously re-arranged to move attackers and victims away from each other. This paper shows that this technique significantly reduces the inductive coupling for the most vulnerable wires neighboring the attacker with zero area and routing resource penalty.
8Â citations
18 May 1971
TL;DR: The major goals of the SYMBOL computer research project have been to provide a more effective man-machine interface and to reduce the total cost of a digital system to the user.
Abstract: The major goals of the SYMBOL computer research project have been to provide a more effective man-machine interface and to reduce the total cost of a digital system to the user. The development of the multi-processing/multi-programming computer architecture with much of the executive system, memory management, and high-level language implemented in hardware is described in other related papers. The SYMBOL project also has investigated low-cost construction techniques suitable for equipment to be used in commercial/industrial environments.
8Â citations
14 Dec 2003
TL;DR: This paper shows a formulation of the swizzling technique and reports on some simulation results to highlight the resulting improvements.
Abstract: On-chip inductive coupling has been shown to depend on the distance wires ran in parallel. It has also been shown to depend on the distance separating an attacker and the victim. This has major effect on global signal busses in high performance microprocessors as they are usually routed as a bundle containing a large number of signals traveling for long distances. A solution has been proposed through a process known as swizzling, where the order of signal wires in the bus is continuously rearranged to move attackers and victims away from each other. This technique has the advantage of reducing the mutual inductance between neighboring wires with zero area or routing resource cost. In this paper, we show a formulation of the swizzling technique and report on some simulation results to highlight the resulting improvements.
8Â citations
08 Aug 2000
TL;DR: A method is introduced to evaluate time domain signals within RLC trees with arbitrary accuracy in response to any input signal by direct truncation of the exact transfer function at different nodes of an RLC tree.
Abstract: A method is introduced to evaluate time domain signals within RLC trees with arbitrary accuracy in response to any input signal. This method depends on finding a low frequency reduced order transfer function by direct truncation of the exact transfer function at different nodes of an RLC tree. The method is numerically accurate for any order of approximation, which permits approximations to be determined with a large number of poles appropriate for approximating RLC trees with underdamped responses. The method is computationally efficient with a complexity linearly proportional to the number of branches in an RLC tree. A common set of poles are determined that characterize the responses at all of the nodes of an RLC tree which further enhances the computational efficiency. Stability is guaranteed by the DTT method for low order approximations with less than 5 poles. Such low order approximations are useful for evaluating monotone responses exhibited by RC circuits.
8Â citations
01 Aug 2014
TL;DR: In this paper, Bounded Uncorrelated Jitter, Random Jitter and Periodic Jitter are examined and a method is proposed to find BUJ in the presence of RJ, by first estimating RJ and then finding BUJ through de-convolution.
Abstract: Although decreasing IC feature size and increasing I/O speed enable better system capability and performance, they also introduce technological challenges. One of the most important challenges is as I/O speed increases: jitter should decrease accordingly to ensure a reasonable bit error rate (BER) for a link system. Precise jitter characterization of signals at critical internal nodes provides valuable information for hardware fault diagnosis and next generation design. Understanding the separate contributions to jitter is challenging in this high speed industrial world. In this paper, Bounded Uncorrelated Jitter (BUJ), Random Jitter (RJ) and Periodic Jitter (PJ) are examined. A method is proposed to find BUJ in the presence of RJ, by first estimating RJ and then finding BUJ through de-convolution. A new tail-fit method is proposed to estimate the probability distribution for RJ. This new tail fit method is applicable for the general signal histogram, while the traditional tail fit method is only valid for the specific or ideal signal histogram.
8Â citations
Cites background from "The Effects of Interconnections on ..."
...BUJ is uncorrelated with the channel’s own data pattern [2]-[4]....
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References
More filters
01 Nov 1954
TL;DR: In this article, a simple configuration of four wires (or two wires and ground) can serve simultaneously as a directional coupler, filter, and transformer, and the coupled lines may be of equal or different impedance.
Abstract: The natural coupling between parallel transmission lines is inherently directional. Very simple and cheap directional couplers can be made which utilize this effect. By introducing appropriate variation of coupling with distance a wide variety of transmission characteristics may be realized, including high-pass (ideally, infinite bandwidth) characteristics. The coupled lines may be of equal or different impedance. Thus, a simple configuration of four wires (or two wires and ground) can serve simultaneously as a directional coupler, filter, and transformer.
215Â citations
IBM1
TL;DR: This computer, like the 704, is aimed at scientific problems such as reactor design, hydrodynamics problems, partial differential equations etc., its instruction set and organization are such that it can handle with ease data-processing problems normally associated with commercial applications, such as processing of alphanumeric fields, sorting, and decimal arithmetic.
Abstract: The Stretch Computer project was started in order to achieve two orders of magnitude of improvement in performance over the then existing 704. Although this computer, like the 704, is aimed at scientific problems such as reactor design, hydrodynamics problems, partial differential equations etc., its instruction set and organization are such that it can handle with ease data-processing problems normally associated with commercial applications, such as processing of alphanumeric fields, sorting, and decimal arithmetic.
76Â citations
[...]
TL;DR: This paper gives a brief description of work originating in the Computer Group at Manchester University, the name given to a large computing system which can include a variety of peripheral equipments, and an extensive store.
Abstract: This paper gives a brief description of work originating in the Computer Group at Manchester University. Atlas is the name given to a large computing system which can include a variety of peripheral equipments, and an extensive store. All the activities of the system are controlled by a program called the supervisor. Several types of store are used, and the addressing system enables a virtually unlimited amount of each to be included. The primary store consists of magnetic cores with a cycle time of under two microseconds, which is effectively reduced by multiple selection mechanisms. The core store is divided into 512 word "pages"; this is also the size of the fixed blocks on drums and magnetic tapes. The core store and drum store are addressed identically, and drum transfers are performed automatically as described in Section 3. There is a fixed store which consists of a wire mesh into which ferrite slugs are inserted; it has a fast read-out time, and is used to hold common routines including routines of the supervisor. A subsidiary core store is used as working space for the supervisor. The V-store is a collective name given to various flip-flops throughout the computer, which can be read, set, and re-set by reading from or writing to particular store addresses.
28Â citations
Book•
[...]
01 Nov 2001
TL;DR: In this article, a brief description of work originating in the Computer Group at Manchester University is given, where the core store is divided into 512 word "pages"; this is also the size of the fixed blocks on drums and magnetic tapes.
Abstract: This paper gives a brief description of work originating in the Computer Group at Manchester University. Atlas is the name given to a large computing system which can include a variety of peripheral equipments, and an extensive store. All the activities of the system are controlled by a program called the supervisor. Several types of store are used, and the addressing system enables a virtually unlimited amount of each to be included. The primary store consists of magnetic cores with a cycle time of under two microseconds, which is effectively reduced by multiple selection mechanisms. The core store is divided into 512 word "pages"; this is also the size of the fixed blocks on drums and magnetic tapes. The core store and drum store are addressed identically, and drum transfers are performed automatically as described in Section 3. There is a fixed store which consists of a wire mesh into which ferrite slugs are inserted; it has a fast read-out time, and is used to hold common routines including routines of the supervisor. A subsidiary core store is used as working space for the supervisor. The V-store is a collective name given to various flip-flops throughout the computer, which can be read, set, and re-set by reading from or writing to particular store addresses.
27Â citations
01 Jan 1960
18Â citations