The Effects of Interconnections on High-Speed Logic Circuits
TL;DR: It is shown that high-speed circuitry must be miniaturized and the implications are discussed.
Abstract: By way of worked examples in typical but somewhat idealized cases the effect on circuit speed of circuit interconnections is studied. The source, calculation and minimization of interconnection crosstalk is also discussed. It is shown that high-speed circuitry must be miniaturized and the implications are discussed.
Citations
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TL;DR: A jitter model to calculate the time difference between the distortion-free and the distorted edge crossings of the victim signal was developed and the worst case timing difference, BUJ/sub p-p/, and an algorithm to generate the histogram distribution of BUJ is developed.
Abstract: Bounded uncorrelated jitter (BUJ), a subcomponent of total jitter, is commonly caused by crosstalk coupling from adjacent interconnects on printed circuit boards (PCB). However, the characteristics of BUJ are still not well understood. Neither a mathematical model of jitter, nor an algorithm to generate histograms for BUJ has been developed to this date. Such a model and algorithm would empower designers to predict BUJ to achieve total jitter budget without lengthy simulations and measurements. In this paper, we first review the characteristics of a crosstalk pulse induced by an aggressor signal on a quiet trace. Then, by applying the superposition principle, a jitter model to calculate the time difference between the distortion-free and the distorted edge crossings of the victim signal was developed. This model is also extended to calculate the worst case timing difference, BUJ/sub p-p/. In addition, an algorithm to generate the histogram distribution of BUJ is also developed. The developed algorithm has fast execution times of 10-20 s, compared to simulation and measurement times of 10-30 min.
45Â citations
Cites background or methods from "The Effects of Interconnections on ..."
...Jarvis in [13] presented the equations to calculate the voltage amplitude of the crosstalk....
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...07 ns, we observed serious discrepancies between the crosstalk-induced pulse shape derived from [13] and that calculated from HSPICE simulations....
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TL;DR: In this article, the effects of inductance on repeater insertion in RLC trees are investigated. And the authors propose an algorithm to insert and size repeaters within an RLC tree to optimize a variety of possible cost functions such as minimizing the maximum path delay, the skew between branches, or a combination of area, power, and delay.
Abstract: The effects of inductance on repeater insertion in RLC trees is the focus of this paper. An algorithm is introduced to insert and size repeaters within an RLC tree to optimize a variety of possible cost functions such as minimizing the maximum path delay, the skew between branches, or a combination of area, power, and delay. The algorithm has a complexity proportional to the square of the number of possible repeater positions and determines a repeater solution that is close to the global minimum. The repeater insertion algorithm is used to insert repeaters within several copper-based interconnect trees to minimize the maximum path delay based on both an RC model and an RLC model. The two buffering solutions are compared using the AS/X dynamic circuit simulator. It is shown that as inductance effects increase, the area and power consumed by the inserted repeaters to minimize the path delays of an RLC tree decreases. By including inductance in the repeater insertion methodology, the interconnect is modeled more accurately as compared to an RC model, permitting average savings in area, power, and delay of 40.8%, 15.6%, and 6.7%, respectively, for a variety of copper-based interconnect trees from a 0.25 /spl mu/m CMOS technology. The average savings in area, power, and delay increases to 62.2%, 57.2%, and 9.4%, respectively, when using five times faster devices with the same interconnect trees.
45Â citations
13 Sep 1998
TL;DR: In this article, a closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 7% of SPICE simulations for a wide range of RLC loads.
Abstract: A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 7% of SPICE simulations for a wide range of RLC loads. This expression is based on the alpha power law for deep submicrometer technologies. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 30% for present on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase, which is expected to have a profound effect on traditional design methodologies. The closed form CMOS delay model is applied to the problem of repeater insertion in RLC interconnect. Closed form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. It is shown that large errors in the repeater design process are encountered if inductance is neglected. Errors up to 30% can occur if repeaters are inserted without considering the effects of inductance. The error between the RC and RLC models increases as the gate parasitic impedances decrease. Thus, the importance of inductance in high performance VLSI design methodologies will increase as technologies scale.
45Â citations
TL;DR: A comparison of the central processing unit (CPU) time and storage requirements for the parallel and deductive fault simulation techniques is presented and the results indicate that the deductive technique requires less CPU time for "loosely sequential" circuits or circuits having large numbers of simulated faults.
Abstract: A comparison of the central processing unit (CPU) time and storage requirements for the parallel and deductive fault simulation techniques is presented. Versions of a parallel and deductive simulator were implemented and the comparison performed on an IBM System/360 Model 67 by simulating representative circuits including shift registers, sequencers, counters, two memory units, and a processor. The results indicate that the deductive technique requires less CPU time for "loosely sequential" circuits or circuits having large numbers of simulated faults (e.g., >1000). The parallel technique is faster for small (e.g., <500 gates) "highly sequential" circuits or for small numbers of simulated faults. The storage required for a parallel simulator, however, can always be less than that required for a deductive simulator. In general, if sufficient memory is available, the deductive simulator is the more cost-effective simulator when a wide range of circuits is to be simulated and only one type of simulator is available. A substantial savings in logic circuit development cost can be realized when the proper simulation technique is used for logic design verification, fault analysis, and the generation of diagnostic data.
42Â citations
TL;DR: The SGT via (SGTV) approach is proposed in which grounded vias are added to the SGT at appropriate locations, and the ratio between the lengths of the horizontal and vertical sections of the guard trace is adjusted to minimize NEXT and FEXT.
Abstract: The reliability of circuits on printed circuit boards (PCBs) in many modern electronic products is afiected by severe noise caused by high-speed and low-voltage operation as well as layout constraints compounded by limited space and high circuit density. Crosstalk is a major noise source that interferes with the signal integrity (SI) in poor PCB layout designs. One common method of reducing crosstalk is the three-width (3-W) rule. The serpentine guard trace (SGT) approach has also been used to reduce crosstalk using two terminal matching resistors on the SGT between the aggressor and victim. Although the SGT approach suppresses far-end crosstalk (FEXT) at the expense of more layout space, it also neglects interference caused by near-end crosstalk (NEXT). In this study, we propose the SGT via (SGTV) approach in which grounded vias are added to the SGT at appropriate locations, and the ratio between the lengths of the horizontal and vertical sections of the guard trace is adjusted to minimize NEXT and FEXT. Frequency domain simulated (measured) results showed that the SGTV approach reduced NEXT by 3.7 (7.65) and 0.83 (1.6)dB as well as FEXT by 5.11 (7.22) and 0.1 (1.98)dB compared to the 3-W and SGT approaches, respectively. In the time domain, simulated (measured) results showed that SGTV reduced NEXT by 34.67% (49.8%) and 27.5% (26.65%) as well as FEXT by 46.78% (56.52%) and 6.91% (24.8%) compared to the 3-W and SGT approaches, respectively.
39Â citations
References
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01 Nov 1954
TL;DR: In this article, a simple configuration of four wires (or two wires and ground) can serve simultaneously as a directional coupler, filter, and transformer, and the coupled lines may be of equal or different impedance.
Abstract: The natural coupling between parallel transmission lines is inherently directional. Very simple and cheap directional couplers can be made which utilize this effect. By introducing appropriate variation of coupling with distance a wide variety of transmission characteristics may be realized, including high-pass (ideally, infinite bandwidth) characteristics. The coupled lines may be of equal or different impedance. Thus, a simple configuration of four wires (or two wires and ground) can serve simultaneously as a directional coupler, filter, and transformer.
215Â citations
IBM1
TL;DR: This computer, like the 704, is aimed at scientific problems such as reactor design, hydrodynamics problems, partial differential equations etc., its instruction set and organization are such that it can handle with ease data-processing problems normally associated with commercial applications, such as processing of alphanumeric fields, sorting, and decimal arithmetic.
Abstract: The Stretch Computer project was started in order to achieve two orders of magnitude of improvement in performance over the then existing 704. Although this computer, like the 704, is aimed at scientific problems such as reactor design, hydrodynamics problems, partial differential equations etc., its instruction set and organization are such that it can handle with ease data-processing problems normally associated with commercial applications, such as processing of alphanumeric fields, sorting, and decimal arithmetic.
76Â citations
[...]
TL;DR: This paper gives a brief description of work originating in the Computer Group at Manchester University, the name given to a large computing system which can include a variety of peripheral equipments, and an extensive store.
Abstract: This paper gives a brief description of work originating in the Computer Group at Manchester University. Atlas is the name given to a large computing system which can include a variety of peripheral equipments, and an extensive store. All the activities of the system are controlled by a program called the supervisor. Several types of store are used, and the addressing system enables a virtually unlimited amount of each to be included. The primary store consists of magnetic cores with a cycle time of under two microseconds, which is effectively reduced by multiple selection mechanisms. The core store is divided into 512 word "pages"; this is also the size of the fixed blocks on drums and magnetic tapes. The core store and drum store are addressed identically, and drum transfers are performed automatically as described in Section 3. There is a fixed store which consists of a wire mesh into which ferrite slugs are inserted; it has a fast read-out time, and is used to hold common routines including routines of the supervisor. A subsidiary core store is used as working space for the supervisor. The V-store is a collective name given to various flip-flops throughout the computer, which can be read, set, and re-set by reading from or writing to particular store addresses.
28Â citations
Book•
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01 Nov 2001
TL;DR: In this article, a brief description of work originating in the Computer Group at Manchester University is given, where the core store is divided into 512 word "pages"; this is also the size of the fixed blocks on drums and magnetic tapes.
Abstract: This paper gives a brief description of work originating in the Computer Group at Manchester University. Atlas is the name given to a large computing system which can include a variety of peripheral equipments, and an extensive store. All the activities of the system are controlled by a program called the supervisor. Several types of store are used, and the addressing system enables a virtually unlimited amount of each to be included. The primary store consists of magnetic cores with a cycle time of under two microseconds, which is effectively reduced by multiple selection mechanisms. The core store is divided into 512 word "pages"; this is also the size of the fixed blocks on drums and magnetic tapes. The core store and drum store are addressed identically, and drum transfers are performed automatically as described in Section 3. There is a fixed store which consists of a wire mesh into which ferrite slugs are inserted; it has a fast read-out time, and is used to hold common routines including routines of the supervisor. A subsidiary core store is used as working space for the supervisor. The V-store is a collective name given to various flip-flops throughout the computer, which can be read, set, and re-set by reading from or writing to particular store addresses.
27Â citations
01 Jan 1960
18Â citations